Three-dimensional memory devices

ABSTRACT

A three-dimensional (3D) memory device is disclosed. The 3D memory device includes a memory stack, a semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack, and a source contact above the memory stack and in contact with the semiconductor layer. A semiconductor plug, in contact with the semiconductor layer, surrounds an end of one of the channel structures. The source contact is electrically connected with the one of the channel structures. At least a portion of the source contact is buried within the semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is continuation of U.S. patent application Ser. No. 16/913,611, filed on Jun. 26, 2020, which is continuation of International Patent Application No. PCT/CN2020/092499, filed on May 27, 2020, entitled “THREE-DIMENSIONAL MEMORY DEVICES,” which is hereby incorporated by reference in its entirety. This application is also related to U.S. patent application Ser. No. 16/913,634, filed on Jun. 26, 2020, entitled “THREE-DIMENSIONAL MEMORY DEVICES,” U.S. patent application Ser. No. 16/913,649, filed on Jun. 26, 2020, entitled “METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES,” and U.S. patent application Ser. No. 16/913,677, filed on Jun. 26, 2020, entitled “METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES,” all of which are hereby incorporated by reference in their entireties.

BACKGROUND

Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and fabrication methods thereof.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells.

The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

SUMMARY

Embodiments of 3D memory devices and methods for forming the same are disclosed herein.

In one example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, an N-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, and a source contact above the memory stack and in contact with the N-type doped semiconductor layer. An upper end of each of the plurality of channel structures is flush with or below a top surface of the N-type doped semiconductor layer.

In another example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, an N-type doped semiconductor layer above the memory stack, and a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer. Each of the plurality of channel structures includes a memory film and a semiconductor channel. An upper end of the memory film is below an upper end of the semiconductor channel. The N-type doped semiconductor layer includes a semiconductor plug surrounding and in contact with a portion of the semiconductor channel. A doping concentration of the semiconductor plugs is different from a doping concentration of the rest of the N-type doped semiconductor layer.

In still another example, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes a memory stack including interleaved conductive layers and dielectric layers, an N-type doped semiconductor layer, and a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer and electrically connected to the peripheral circuit. The N-type doped semiconductor layer includes a semiconductor plug surrounding a portion of each of the plurality of channel structures extending into the N-type doped semiconductor layer. A doping concentration of the semiconductor plugs is different from a doping concentration of the rest of the N-type doped semiconductor layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1 illustrates a side view of a cross-section of an exemplary 3D memory device, according to some embodiments of the present disclosure.

FIG. 2 illustrates a side view of a cross-section of another exemplary 3D memory device, according to some embodiments of the present disclosure.

FIGS. 3A-3N illustrate a fabrication process for forming an exemplary 3D memory device, according to some embodiments of the present disclosure.

FIGS. 4A-4O illustrate a fabrication process for forming another exemplary 3D memory device, according to some embodiments of the present disclosure.

FIGS. 5A illustrates a flowchart of a method for forming an exemplary 3D memory device, according to some embodiments of the present disclosure.

FIGS. 5B illustrates a flowchart of another method for forming an exemplary 3D memory device, according to some embodiments of the present disclosure.

FIGS. 6A illustrates a flowchart of a method for forming another exemplary 3D memory device, according to some embodiments of the present disclosure.

FIGS. 6B illustrates a flowchart of another method for forming another exemplary 3D memory device, according to some embodiments of the present disclosure.

Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something).

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

As used herein, the term “nominal/nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

As used herein, the term “3D memory device” refers to a semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND memory strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate.

In some 3D memory devices, such as 3D NAND memory devices, slit structures (e.g., gate line slits (GLSs)) are used for providing electrical connections to the source of the memory array, such as array common source (ACS), from the front side of the devices. The front side source contacts, however, can affect the electrical performance of the 3D memory devices by introducing both leakage current and parasitic capacitance between the word lines and the source contacts, even with the presence of spacers in between. The formation of the spacers also complicates the fabrication process. Besides affecting the electrical performance, the slit structures usually include wall-shaped polysilicon and/or metal fillings, which can introduce local stress to cause wafer bow or warp, thereby reducing the production yield.

Moreover, in some 3D NAND memory devices, semiconductor plugs are selectively grown to surround the sidewalls of channel structures, e.g., known as sidewall selective epitaxial growth (SEG). Compared with another type of semiconductor plugs that are formed at the lower end of the channel structures, e.g., bottom SEG, the formation of sidewall SEG avoids the etching of the memory film and semiconductor channel at the bottom surface of channel holes (also known as “SONO” punch), thereby increasing the process window, in particular when fabricating 3D NAND memory devices with advanced technologies, such as having 96 or more levels with a multi-deck architecture. Sidewall SEGs are usually formed by replacing a sacrificial layer between the substrate and stack structure with the sidewall SEGs, which involves multiple deposition and etching processes through the slit openings. However, as the levels of 3D NAND memory devices continue increasing, the aspect ratio of the slit openings extending through the stack structure becomes larger, making the deposition and etching processes through the slit openings more challenging and undesirable for forming the sidewall SEGs using the known approach due to the increased cost and reduced yield.

Various embodiments in accordance with the present disclosure provide 3D memory devices with backside source contacts. By moving the source contacts from the front side to the backside, the cost per memory cell can be reduced as the effective memory cell array area can be increased, and the spacers formation process can be skipped. The device performance can be improved as well, for example, by avoiding the leakage current and parasitic capacitance between the word lines and the source contacts and by reducing the local stress caused by the front side slit structures (as source contacts). The sidewall SEGs (e.g., semiconductor plugs) can be formed from the backside of the substrate to avoid any deposition or etching process through the openings extending through the stack structure at the front side of the substrate. As a result, the complexity and cost of the fabrication process can be reduced, and the product yield can be increased. Also, as the fabrication process of the sidewall SEGs is no longer affected by the aspect ratio of the openings through the stack structure, i.e., not limited by the levels of the memory stack, the scalability of the 3D memory devices can be improved as well.

In some embodiments, the substrate on which the memory stack is formed is removed from the backside to expose the channel structures prior to the formation of the sidewall SEGs. Thus, the selection of the substrate can be expanded, for example, to dummy wafers to reduce the cost or to silicon on insulator (SOI) wafers to simplify the fabrication process. The removal of the substrate can also avoid the challenging issue of thickness uniformity control in known methods using the backside thinning process.

Various 3D memory device architectures and fabrication methods thereof, for example, with different erase operation mechanisms, are disclosed in the present disclosure to accommodate different requirements and applications. In some embodiments, the sidewall SEGs are parts of an N-type doped semiconductor layer to enable gate-induced-drain-leakage (GIDL) erasing by the 3D memory device. In some embodiments, the sidewall SEGs are parts of a P-type doped semiconductor layer to enable P-well bulk erasing by the 3D memory device.

FIG. 1 illustrates a side view of a cross-section of an exemplary 3D memory device 100, according to some embodiments of the present disclosure. In some embodiments, 3D memory device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked over first semiconductor structure 102. First and second semiconductor structures 102 and 104 are jointed at a bonding interface 106 therebetween, according to some embodiments. As shown in FIG. 1 , first semiconductor structure 102 can include a substrate 101, which can include silicon (e.g., single crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), SOI, or any other suitable materials.

First semiconductor structure 102 of 3D memory device 100 can include peripheral circuits 108 on substrate 101. It is noted that x and y axes are included in FIG. 1 to further illustrate the spatial relationship of the components in 3D memory device 100 having substrate 101. Substrate 101 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (i.e., the lateral direction). As used herein, whether one component (e.g., a layer or a device) is “on,” “above,” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D memory device 100) is determined relative to the substrate of the semiconductor device (e.g., substrate 101) in they-direction (i.e., the vertical direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing spatial relationships is applied throughout the present disclosure.

In some embodiments, peripheral circuit 108 is configured to control and sense 3D memory device 100. Peripheral circuit 108 can be any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of 3D memory device 100 including, but not limited to, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuits 108 can include transistors formed “on” substrate 101, in which the entirety or part of the transistors are formed in substrate 101 (e.g., below the top surface of substrate 101) and/or directly on substrate 101. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of the transistors) can be formed in substrate 101 as well. The transistors are high-speed with advanced logic processes (e.g., technology nodes of 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.), according to some embodiments. It is understood that in some embodiments, peripheral circuit 108 may further include any other circuits compatible with the advanced logic processes including logic circuits, such as processors and programmable logic devices (PLDs), or memory circuits, such as static random-access memory (SRAM) and dynamic RAM (DRAM).

In some embodiments, first semiconductor structure 102 of 3D memory device 100 further includes an interconnect layer (not shown) above peripheral circuits 108 to transfer electrical signals to and from peripheral circuits 108. The interconnect layer can include a plurality of interconnects (also referred to herein as “contacts”), including lateral interconnect lines and vertical interconnect access (VIA) contacts. As used herein, the term “interconnects” can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer can further include one or more interlayer dielectric (ILD) layers (also known as “intermetal dielectric (IMD) layers”) in which the interconnect lines and VIA contacts can form. That is, the interconnect layer can include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

As shown in FIG. 1 , first semiconductor structure 102 of 3D memory device 100 can further include a bonding layer 110 at bonding interface 106 and above the interconnect layer and peripheral circuits 108. Bonding layer 110 can include a plurality of bonding contacts 111 and dielectrics electrically isolating bonding contacts 111. Bonding contacts 111 can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer 110 can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts 111 and surrounding dielectrics in bonding layer 110 can be used for hybrid bonding.

Similarly, as shown in FIG. 1 , second semiconductor structure 104 of 3D memory device 100 can also include a bonding layer 112 at bonding interface 106 and above bonding layer 110 of first semiconductor structure 102. Bonding layer 112 can include a plurality of bonding contacts 113 and dielectrics electrically isolating bonding contacts 113. Bonding contacts 113 can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer 112 can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts 113 and surrounding dielectrics in bonding layer 112 can be used for hybrid bonding. Bonding contacts 113 are in contact with bonding contacts 111 at bonding interface 106, according to some embodiments.

As described below in detail, second semiconductor structure 104 can be bonded on top of first semiconductor structure 102 in a face-to-face manner at bonding interface 106. In some embodiments, bonding interface 106 is disposed between bonding layers 110 and 112 as a result of hybrid bonding (also known as “metal/dielectric hybrid bonding”), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, bonding interface 106 is the place at which bonding layers 112 and 110 are met and bonded. In practice, bonding interface 106 can be a layer with a certain thickness that includes the top surface of bonding layer 110 of first semiconductor structure 102 and the bottom surface of bonding layer 112 of second semiconductor structure 104.

In some embodiments, second semiconductor structure 104 of 3D memory device 100 further includes an interconnect layer (not shown) above bonding layer 112 to transfer electrical signals. The interconnect layer can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which the interconnect lines and VIA contacts can form. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

In some embodiments, 3D memory device 100 is a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown in FIG. 1 , second semiconductor structure 104 of 3D memory device 100 can include an array of channel structures 124 functioning as the array of NAND memory strings. As shown in FIG. 1 , each channel structure 124 can extend vertically through a plurality of pairs each including a conductive layer 116 and a dielectric layer 118. The interleaved conductive layers 116 and dielectric layers 118 are part of a memory stack 114. The number of the pairs of conductive layers 116 and dielectric layers 118 in memory stack 114 (e.g., 32, 64, 96, 128, 160, 192, 224, 256, or more) determines the number of memory cells in 3D memory device 100. It is understood that in some embodiments, memory stack 114 may have a multi-deck architecture (not shown), which includes a plurality of memory decks stacked over one another. The numbers of the pairs of conductive layers 116 and dielectric layers 118 in each memory deck can be the same or different.

Memory stack 114 can include a plurality of interleaved conductive layers 116 and dielectric layers 118. Conductive layers 116 and dielectric layers 118 in memory stack 114 can alternate in the vertical direction. In other words, except the ones at the top or bottom of memory stack 114, each conductive layer 116 can be adjoined by two dielectric layers 118 on both sides, and each dielectric layer 118 can be adjoined by two conductive layers 116 on both sides. Conductive layers 116 can include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each conductive layer 116 can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of conductive layer 116 can extend laterally as a word line, ending at one or more staircase structures of memory stack 114. Dielectric layers 118 can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in FIG. 1 , second semiconductor structure 104 of 3D memory device 100 can also include an N-type doped semiconductor plug 120 above memory stack 114. N-type doped semiconductor layer 120 can be an example of the “sidewall SEG” as described above. N-type doped semiconductor layer 120 can include a semiconductor material, such as silicon. In some embodiments, N-type doped semiconductor layer 120 includes polysilicon formed by deposition techniques, as described below in detail. In some embodiments, N-type doped semiconductor layer 120 includes single crystalline silicon, such as the device layer of an SOI wafer, as described below in detail. N-type doped semiconductor layer 120 can be doped with any suitable N-type dopants, such as phosphorus (P), arsenic (Ar), or antimony (Sb), which contribute free electrons and increase the conductivity of the intrinsic semiconductor. For example, N-type doped semiconductor layer 120 may be a polysilicon layer doped with N-type dopant(s), such as P, Ar, or Sb. In some embodiments, N-type doped semiconductor layer 120 is a single polysilicon layer with a uniform doping concentration profile in the vertical direction, as opposed to having multiple polysilicon sub-layers with nonuniform doping concentrations at their interfaces (e.g., a sudden doping concentration change at an interface between two sub-layers). It is understood that the doping concentration of the N-type dopant(s) of N-type doped semiconductor layer 120 may still gradually change in the vertical direction as long as there are not any sudden doping concentration changes that can distinguish two or more sub-layers by doping concentration variations.

In some embodiments, each channel structure 124 includes a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel 128) and a composite dielectric layer (e.g., as a memory film 126). In some embodiments, semiconductor channel 128 includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, memory film 126 is a composite layer including a tunneling layer, a storage layer (also known as a “charge trap layer”), and a blocking layer. The remaining space of channel structure 124 can be partially or fully filled with a capping layer including dielectric materials, such as silicon oxide, and/or an air gap. Channel structure 124 can have a cylinder shape (e.g., a pillar shape). The capping layer, semiconductor channel 128, the tunneling layer, storage layer, and blocking layer of memory film 126 are arranged radially from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. In one example, memory film 126 can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

In some embodiments, channel structure 124 further includes a channel plug 129 in the bottom portion (e.g., at the lower end) of channel structure 124. As used herein, the “upper end” of a component (e.g., channel structure 124) is the end farther away from substrate 101 in the y-direction, and the “lower end” of the component (e.g., channel structure 124) is the end closer to substrate 101 in the y-direction when substrate 101 is positioned in the lowest plane of 3D memory device 100. Channel plug 129 can include semiconductor materials (e.g., polysilicon). In some embodiments, channel plug 129 functions as the drain of the NAND memory string.

As shown in FIG. 1 , each channel structure 124 can extend vertically through interleaved conductive layers 116 and dielectric layers 118 of memory stack 114 into N-type doped semiconductor layer 120. The upper end of each channel structure 124 can be flush with or below the top surface of N-type doped semiconductor layer 120. That is, channel structure 124 does not extend beyond the top surface of N-type doped semiconductor layer 120, according to some embodiments. In some embodiments, the upper end of memory film 126 is below the upper end of semiconductor channel 128 in channel structure 124, as shown in FIG. 1 . In some embodiments, the upper end of memory film 126 is below the top surface of N-type doped semiconductor layer 120, and the upper end of semiconductor channel 128 is flush with or below the top surface of N-type doped semiconductor layer 120. For example, as shown in FIG. 1 , memory film 126 may end at the bottom surface of N-type doped semiconductor layer 120, while semiconductor channel 128 may extend above the bottom surface of N-type doped semiconductor layer 120, such that N-type doped semiconductor layer 120 may surround and in contact with a top portion 127 of semiconductor channel 128 extending into N-type doped semiconductor layer 120. In some embodiments, the doping concentration of top portion 127 of semiconductor channel 128 extending into N-type doped semiconductor layer 120 is different from the doping concentration of the rest of semiconductor channel 128. For example, semiconductor channel 128 may include undoped polysilicon except top portion 127, which may include doped polysilicon to increase its conductivity in forming an electrical connection with the surrounding N-type doped semiconductor layer 120.

In some embodiments, N-type doped semiconductor layer 120 includes semiconductor plugs 122 each surrounding and in contact with top portion 127 of respective semiconductor channel 128 of channel structure 124 extending into N-type doped semiconductor layer 120. Semiconductor plug 122 includes doped polysilicon, for example, N-type doped polysilicon, according to some embodiments. The doping concentration of semiconductor plugs 122 can be different from the doping concentration of the rest of N-type doped semiconductor layer 120 since semiconductor plugs 122 can be formed in a later process after the formation of the rest of N-type doped semiconductor layer 120, as described below in detail. In some embodiments, semiconductor plugs 122 include polysilicon (e.g., N-type doped polysilicon), and the rest of N-type doped semiconductor layer 120 includes single crystalline silicon (e.g., N-type doped single crystalline silicon). In some embodiments, semiconductor plugs 122 include polysilicon (e.g., N-type doped polysilicon), and the rest of N-type doped semiconductor layer 120 includes polysilicon (e.g., N-type doped polysilicon), but with doping centration different from that of semiconductor plugs 122.

Each semiconductor plug 122 can surround and in contact with the sidewall of top portion 127 of respective semiconductor channel 128. As a result, semiconductor plugs 122 in N-type doped semiconductor layer 120 can work as a “sidewall SEG (e.g., semiconductor plug)” of channel structure 124 to replace the “bottom SEG (e.g., semiconductor plug).” Moreover, as described below in detail, the formation of semiconductor plugs 122 occurs at the opposite side of memory stack 114, which can avoid any deposition or etching process through openings extending through memory stack 114, thereby reducing the fabrication complexity and cost and increasing the yield and vertical scalability. Depending on the relative position of the upper end of semiconductor channel 128 of each channel structure 124 with respect to the top surface of N-type doped semiconductor layer 120, semiconductor plug 122 may be formed above and in contact with the upper end of semiconductor channel 128 as well, for example, as shown in FIG. 1 , when the upper end of semiconductor channel 128 is below the top surface of N-type doped semiconductor layer 120. It is understood that in other examples in which the upper end of semiconductor channel 128 is flush with the top surface of N-type doped semiconductor layer 120, semiconductor plug 122 may be formed surrounding and in contact with the sidewall of top portion 127 of semiconductor channel 128 only.

Nevertheless, N-type doped semiconductor layer 120 surrounding top portion 127 of semiconductor channels 128 of channel structures 124 with semiconductor plugs 122 (e.g., as sidewall SEGs) can enable GIDL-assisted body biasing for erase operations for 3D memory device 100. The GIDL around the source select gate of the NAND memory string can generate hole current into the NAND memory string to raise the body potential for erase operations.

As shown in FIG. 1 , second semiconductor structure 104 of 3D memory device 100 can further include insulating structures 130 each extending vertically through interleaved conductive layers 116 and dielectric layers 118 of memory stack 114. Different from channel structure 124 that extends further into N-type doped semiconductor layer 120, insulating structures 130 stops at the bottom surface of N-type doped semiconductor layer 120, i.e., does not extend vertically into N-type doped semiconductor layer 120, according to some embodiments. That is, the top surface of insulating structure 130 can be flush with the bottom surface of N-type doped semiconductor layer 120. Each insulating structure 130 can also extend laterally to separate channel structures 124 into a plurality of blocks. That is, memory stack 114 can be divided into a plurality of memory blocks by insulating structures 130, such that the array of channel structures 124 can be separated into each memory block. Different from the slit structures in existing 3D NAND memory devices described above, which include front side ACS contacts, insulating structure 130 does not include any contact therein (i.e., not functioning as the source contact) and thus, does not introduce parasitic capacitance and leakage current with conductive layers 116 (including word lines), according to some embodiments. In some embodiments, each insulating structure 130 includes an opening (e.g., a slit) filled with one or more dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 130 may be filled with silicon oxide.

Moreover, as described below in detail, because the opening for forming insulating structure 130 is not used for forming N-type doped semiconductor layer 120 and semiconductor plugs 122 therein (e.g., as sidewall SEGs), the increased aspect ratio of the opening as the number of interleaved conductive layers 116 and dielectric layers 118 increases would not affect the formation of N-type doped semiconductor layer 120 and semiconductor plugs 122 therein.

Instead of the front side source contacts, 3D memory device 100 can include a backside source contact 132 above memory stack 114 and in contact with N-type doped semiconductor layer 120, as shown in FIG. 1 . Source contact 132 and memory stack 114 (and insulating structure 130 therethrough) can be disposed at opposites sides of N-type doped semiconductor layer 120 and thus, viewed as a “backside” source contact. In some embodiments, source contact 132 is electrically connected to semiconductor channel 128 of channel structure 124 through semiconductor plug 122 of N-type doped semiconductor layer 120. In some embodiments, source contact 132 is not laterally aligned with insulating structure 130, but approximate to channel structure 124 to reduce the resistance of the electrical connection therebetween. For example, source contact 132 may be laterally between insulating structure 130 and channel structure 124 (e.g., in the x-direction in FIG. 1 ). Source contacts 132 can include any suitable types of contacts. In some embodiments, source contacts 132 include a VIA contact. In some embodiments, source contacts 132 include a wall-shaped contact extending laterally. Source contact 132 can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

As shown in FIG. 1 , 3D memory device 100 can further include a BEOL interconnect layer 133 above and electrically connected to source contact 132 for pad-out, e.g., transferring electrical signals between 3D memory device 100 and external circuits. In some embodiments, interconnect layer 133 includes one or more ILD layers 134 on N-type doped semiconductor layer 120 and a redistribution layer 136 on ILD layers 134. The upper end of source contact 132 is flush with the top surface of ILD layers 134, and the bottom surface of redistribution layer 136, and source contact 132 extends vertically through ILD layers 134 into N-type doped semiconductor layer 120, according to some embodiments. ILD layers 134 in interconnect layer 133 can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Redistribution layer 136 in interconnect layer 133 can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, redistribution layer 136 includes Al. In some embodiments, interconnect layer 133 further includes a passivation layer 138 as the outmost layer for passivation and protection of 3D memory device 100. Part of redistribution layer 136 can be exposed from passivation layer 138 as contact pads 140. That is, interconnect layer 133 of 3D memory device 100 can also include contact pads 140 for wire bonding and/or bonding with an interposer.

In some embodiments, second semiconductor structure 104 of 3D memory device 100 further includes contacts 142 and 144 through N-type doped semiconductor layer 120. As N-type doped semiconductor layer 120 can be a thinned substrate, for example, the device layer of an SOI wafer, contacts 142 and 144 are through silicon contacts (TSCs), according to some embodiments. In some embodiments, contact 142 extends through N-type doped semiconductor layer 120 and ILD layers 134 to be in contact with redistribution layer 136, such that N-type doped semiconductor layer 120 is electrically connected to contact 142 through source contact 132 and redistribution layer 136 of interconnect layer 133. In some embodiments, contact 144 extends through N-type doped semiconductor layer 120 and ILD layers 134 to be in contact with contact pad 140. Contacts 142 and 144 each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, at least contact 144 further includes a spacer (e.g., a dielectric layer) to electrically separate contact 144 from N-type doped semiconductor layer 120.

In some embodiments, 3D memory device 100 further includes peripheral contacts 146 and 148 each extending vertically outside of memory stack 114. Each peripheral contact 146 or 148 can have a depth greater than the depth of memory stack 114 to extend vertically from bonding layer 112 to N-type doped semiconductor layer 120 in a peripheral region that is outside of memory stack 114. In some embodiments, peripheral contact 146 is below and in contact with contact 142, such that N-type doped semiconductor layer 120 is electrically connected to peripheral circuit 108 in first semiconductor structure 102 through at least source contact 132, interconnect layer 133, contact 142, and peripheral contact 146. In some embodiments, peripheral contact 148 is below and in contact with contact 144, such that peripheral circuit 108 in first semiconductor structure 102 is electrically connected to contact pad 140 for pad-out through at least contact 144 and peripheral contact 148. Peripheral contacts 146 and 148 each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

As shown in FIG. 1 , 3D memory device 100 also includes a variety of local contacts (also known as “C1”) as part of the interconnect structure, which are in contact with a structure in memory stack 114 directly. In some embodiments, the local contacts include channel local contacts 150 each below and in contact with the lower end of respective channel structure 124. Each channel local contact 150 can be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts further include word line local contacts 152 each below and in contact with respective conductive layer 116 (including a word line) at the staircase structure of memory stack 114 for word line fan-out. Local contacts, such as channel local contacts 150 and word line local contacts 152, can be electrically connected to peripheral circuits 108 of first semiconductor structure 102 through at least bonding layers 112 and 110. Local contacts, such as channel local contacts 150 and word line local contacts 152, each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

FIG. 2 illustrates a side view of a cross-section of another exemplary 3D memory device 200, according to some embodiments of the present disclosure. In some embodiments, 3D memory device 200 is a bonded chip including a first semiconductor structure 202 and a second semiconductor structure 204 stacked over first semiconductor structure 202. First and second semiconductor structures 202 and 204 are jointed at a bonding interface 206 therebetween, according to some embodiments. As shown in FIG. 2 , first semiconductor structure 202 can include a substrate 201, which can include silicon (e.g., single crystalline silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable materials.

First semiconductor structure 202 of 3D memory device 200 can include peripheral circuits 208 on substrate 201. In some embodiments, peripheral circuit 208 is configured to control and sense 3D memory device 200. Peripheral circuit 208 can be any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of 3D memory device 200 including, but not limited to, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuits 208 can include transistors formed “on” substrate 201, in which the entirety or part of the transistors are formed in substrate 201 (e.g., below the top surface of substrate 201) and/or directly on substrate 201. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of the transistors) can be formed in substrate 201 as well. The transistors are high-speed with advanced logic processes (e.g., technology nodes of 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.), according to some embodiments. It is understood that in some embodiments, peripheral circuit 208 may further include any other circuits compatible with the advanced logic processes including logic circuits, such as processors and PLDs, or memory circuits, such as SRAM and DRAM.

In some embodiments, first semiconductor structure 202 of 3D memory device 200 further includes an interconnect layer (not shown) above peripheral circuits 208 to transfer electrical signals to and from peripheral circuits 208. The interconnect layer can include a plurality of interconnects (also referred to herein as “contacts”), including lateral interconnect lines and VIA contacts. As used herein, the term “interconnects” can broadly include any suitable types of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers (also known as “(IMD layers”) in which the interconnect lines and VIA contacts can form. That is, the interconnect layer can include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

As shown in FIG. 2 , first semiconductor structure 202 of 3D memory device 200 can further include a bonding layer 210 at bonding interface 206 and above the interconnect layer and peripheral circuits 208. Bonding layer 210 can include a plurality of bonding contacts 211 and dielectrics electrically isolating bonding contacts 211. Bonding contacts 211 can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer 210 can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts 211 and surrounding dielectrics in bonding layer 210 can be used for hybrid bonding.

Similarly, as shown in FIG. 2 , second semiconductor structure 204 of 3D memory device 200 can also include a bonding layer 212 at bonding interface 206 and above bonding layer 210 of first semiconductor structure 202. Bonding layer 212 can include a plurality of bonding contacts 213 and dielectrics electrically isolating bonding contacts 213. Bonding contacts 213 can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer 212 can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts 213 and surrounding dielectrics in bonding layer 212 can be used for hybrid bonding. Bonding contacts 213 are in contact with bonding contacts 211 at bonding interface 206, according to some embodiments.

As described below in detail, second semiconductor structure 204 can be bonded on top of first semiconductor structure 202 in a face-to-face manner at bonding interface 206. In some embodiments, bonding interface 206 is disposed between bonding layers 210 and 212 as a result of hybrid bonding (also known as “metal/dielectric hybrid bonding”), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, bonding interface 206 is the place at which bonding layers 212 and 210 are met and bonded. In practice, bonding interface 206 can be a layer with a certain thickness that includes the top surface of bonding layer 210 of first semiconductor structure 202 and the bottom surface of bonding layer 212 of second semiconductor structure 204.

In some embodiments, second semiconductor structure 204 of 3D memory device 200 further includes an interconnect layer (not shown) above bonding layer 212 to transfer electrical signals. The interconnect layer can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which the interconnect lines and VIA contacts can form. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

In some embodiments, 3D memory device 200 is a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown in FIG. 2 , second semiconductor structure 204 of 3D memory device 200 can include an array of channel structures 224 functioning as the array of NAND memory strings. As shown in FIG. 2 , each channel structure 224 can extend vertically through a plurality of pairs each including a conductive layer 216 and a dielectric layer 218. The interleaved conductive layers 216 and dielectric layers 218 are part of a memory stack 214. The number of the pairs of conductive layers 216 and dielectric layers 218 in memory stack 214 (e.g., 32, 64, 96, 128, 160, 192, 224, 256, or more) determines the number of memory cells in 3D memory device 200. It is understood that in some embodiments, memory stack 214 may have a multi-deck architecture (not shown), which includes a plurality of memory decks stacked over one another. The numbers of the pairs of conductive layers 216 and dielectric layers 218 in each memory deck can be the same or different.

Memory stack 214 can include a plurality of interleaved conductive layers 216 and dielectric layers 218. Conductive layers 216 and dielectric layers 218 in memory stack 214 can alternate in the vertical direction. In other words, except the ones at the top or bottom of memory stack 214, each conductive layer 216 can be adjoined by two dielectric layers 218 on both sides, and each dielectric layer 218 can be adjoined by two conductive layers 216 on both sides. Conductive layers 216 can include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each conductive layer 216 can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of conductive layer 216 can extend laterally as a word line, ending at one or more staircase structures of memory stack 214. Dielectric layers 218 can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in FIG. 2 , second semiconductor structure 204 of 3D memory device 200 can also include a P-type doped semiconductor layer 220 above memory stack 114. P-type doped semiconductor layer 220 can be an example of the “sidewall SEG” as described above. P-type doped semiconductor layer 220 can include a semiconductor material, such as silicon. In some embodiments, P-type doped semiconductor layer 220 includes polysilicon formed by deposition techniques, as described below in detail. In some embodiments, P-type doped semiconductor layer 220 includes single crystalline silicon, such as the device layer of an SOI wafer, as described below in detail. P-type doped semiconductor layer 220 can be doped with any suitable P-type dopants, such as boron (B), gallium (Ga), or aluminum (Al), to an intrinsic semiconductor creates deficiencies of valence electrons, called “holes.” For example, P-type doped semiconductor layer 220 may be a polysilicon layer doped with P-type dopant(s), such as P, Ar, or Sb. In some embodiments, P-type doped semiconductor layer 220 is a single polysilicon layer with a uniform doping concentration profile in the vertical direction, as opposed to having multiple polysilicon sub-layers with nonuniform doping concentrations at their interfaces (e.g., a sudden doping concentration change at an interface between two sub-layers). It is understood that the doping concentration of the P-type dopant(s) of P-type doped semiconductor layer 220 may still gradually change in the vertical direction as long as there are not any sudden doping concentration changes that can distinguish two or more sub-layers by doping concentration variations.

In some embodiments, second semiconductor structure 204 of 3D memory device 200 further includes an N-well 221 in P-type doped semiconductor layer 220. N-well 221 can be doped with any suitable N-type dopants, such as P, Ar, or Sb, which contribute free electrons and increase the conductivity of the intrinsic semiconductor. In some embodiments, N-well 221 is doped from the bottom surface of P-type doped semiconductor layer 220. It is understood that N-well 221 may extend vertically in the entire thickness of P-type doped semiconductor layer 220, i.e., to the top surface of P-type doped semiconductor layer 220, or part of the entire thickness of P-type doped semiconductor layer 220.

In some embodiments, each channel structure 224 includes a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel 228) and a composite dielectric layer (e.g., as a memory film 226). In some embodiments, semiconductor channel 228 includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, memory film 226 is a composite layer including a tunneling layer, a storage layer (also known as a “charge trap layer”), and a blocking layer. The remaining space of channel structure 224 can be partially or fully filled with a capping layer including dielectric materials, such as silicon oxide, and/or an air gap. Channel structure 224 can have a cylinder shape (e.g., a pillar shape). The capping layer, semiconductor channel 228, the tunneling layer, storage layer, and blocking layer of memory film 226 are arranged radially from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. In one example, memory film 226 can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

In some embodiments, channel structure 224 further includes a channel plug 227 in the bottom portion (e.g., at the lower end) of channel structure 224. As used herein, the “upper end” of a component (e.g., channel structure 224) is the end farther away from substrate 201 in the y-direction, and the “lower end” of the component (e.g., channel structure 224) is the end closer to substrate 201 in the y-direction when substrate 201 is positioned in the lowest plane of 3D memory device 200. Channel plug 227 can include semiconductor materials (e.g., polysilicon). In some embodiments, channel plug 227 functions as the drain of the NAND memory string.

As shown in FIG. 2 , each channel structure 224 can extend vertically through interleaved conductive layers 216 and dielectric layers 218 of memory stack 214 into P-type doped semiconductor layer 220. The upper end of each channel structure 224 can be flush with or below the top surface of P-type doped semiconductor layer 220. That is, channel structure 224 does not extend beyond the top surface of P-type doped semiconductor layer 220, according to some embodiments. In some embodiments, the upper end of memory film 226 is below the upper end of semiconductor channel 228 in channel structure 224, as shown in FIG. 2 . In some embodiments, the upper end of memory film 226 is below the top surface of P-type doped semiconductor layer 220, and the upper end of semiconductor channel 228 is flush with or below the top surface of P-type doped semiconductor layer 220. For example, as shown in FIG. 2 , memory film 226 may end at the bottom surface of P-type doped semiconductor layer 220, while semiconductor channel 228 may extend above the bottom surface of P-type doped semiconductor layer 220, such that P-type doped semiconductor layer 220 may surround and in contact with a top portion 229 of semiconductor channel 228 extending into P-type doped semiconductor layer 220. In some embodiments, the doping concentration of top portion 229 of semiconductor channel 228 extending into P-type doped semiconductor layer 220 is different from the doping concentration of the rest of semiconductor channel 228. For example, semiconductor channel 228 may include undoped polysilicon except top portion 229, which may include doped polysilicon to increase its conductivity in forming an electrical connection with surrounding P-type doped semiconductor layer 220.

In some embodiments, P-type doped semiconductor layer 220 includes semiconductor plugs 222 each surrounding and in contact with top portion 229 of respective semiconductor channel 228 of channel structure 224 extending into P-type doped semiconductor layer 220. Semiconductor plug 222 includes doped polysilicon, for example, P-type doped polysilicon, according to some embodiments. The doping concentration of semiconductor plugs 222 can be different from the doping concentration of the rest of P-type doped semiconductor layer 220 since semiconductor plugs 222 can be formed in a later process after the formation of the rest of P-type doped semiconductor layer 220, as described below in detail. In some embodiments, semiconductor plugs 222 include polysilicon (e.g., P-type doped polysilicon), and the rest of P-type doped semiconductor layer 220 includes single crystalline silicon (e.g., P-type doped single crystalline silicon). In some embodiments, semiconductor plugs 222 include polysilicon (e.g., P-type doped polysilicon), and the rest of P-type doped semiconductor layer 220 includes polysilicon (e.g., P-type doped polysilicon), but with doping centration different from that of semiconductor plugs 222.

Each semiconductor plug 222 can surround and in contact with the sidewall of top portion 229 of respective semiconductor channel 228. As a result, semiconductor plugs 222 in P-type doped semiconductor layer 220 can work as a “sidewall SEG (e.g., semiconductor plug)” of channel structure 224 to replace the “bottom SEG (e.g., semiconductor plug).” Moreover, as described below in detail, the formation of semiconductor plugs 222 occurs at the opposite side of memory stack 214, which can avoid any deposition or etching process through openings extending through memory stack 214, thereby reducing the fabrication complexity and cost and increasing the yield and vertical scalability. Depending on the relative position of the upper end of semiconductor channel 228 of each channel structure 224 with respect to the top surface of P-type doped semiconductor layer 220, semiconductor plug 222 may be formed above and in contact with the upper end of semiconductor channel 228 as well, for example, as shown in FIG. 2 , when the upper end of semiconductor channel 228 is below the top surface of P-type doped semiconductor layer 220. It is understood that in other examples in which the upper end of semiconductor channel 228 is flush with the top surface of P-type doped semiconductor layer 220, semiconductor plug 222 may be formed surrounding and in contact with the sidewall of top portion 229 of semiconductor channel 228 only.

Nevertheless, P-type doped semiconductor layer 220 surrounding top portion 229 of semiconductor channels 228 of channel structures 224 with semiconductor plugs 222 (e.g., as sidewall SEGs) can enable P-well bulk erase operations for 3D memory device 200. The design of the 3D memory device 200 disclosed herein can achieve the separation of the hole current path and the electron current path for forming erase operations and read operations, respectively. In some embodiments, 3D memory device 200 is configured to form an electron current path between the electron source (e.g., N-well 221) and semiconductor channel 228 of channel structure 224 to provide electrons to the NAND memory string when performing a read operation, according to some embodiments. Conversely, 3D memory device 200 is configured to form a hole current path between the hole source (e.g., P-type doped semiconductor layer 220) and semiconductor channel 228 of channel structure 224 to provide holes to the NAND memory string when performing a P-well bulk erase operation, according to some embodiments.

As shown in FIG. 2 , second semiconductor structure 204 of 3D memory device 200 can further include insulating structures 230 each extending vertically through interleaved conductive layers 216 and dielectric layers 218 of memory stack 214. Different from channel structure 224 that extends further into P-type doped semiconductor layer 220, insulating structures 230 stops at the bottom surface of P-type doped semiconductor layer 220, i.e., does not extend vertically into P-type doped semiconductor layer 220, according to some embodiments. That is, the top surface of insulating structure 230 can be flush with the bottom surface of P-type doped semiconductor layer 220. Each insulating structure 230 can also extend laterally to separate channel structures 224 into a plurality of blocks. That is, memory stack 214 can be divided into a plurality of memory blocks by insulating structures 230, such that the array of channel structures 224 can be separated into each memory block. Different from the slit structures in existing 3D NAND memory devices described above, which include front side ACS contacts, insulating structure 230 does not include any contact therein (i.e., not functioning as the source contact) and thus, does not introduce parasitic capacitance and leakage current with conductive layers 216 (including word lines), according to some embodiments. In some embodiments, each insulating structure 230 includes an opening (e.g., a slit) filled with one or more dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 230 may be filled with silicon oxide.

Moreover, as described below in detail, because the opening for forming insulating structure 230 is not used for forming P-type doped semiconductor layer 220 and semiconductor plugs 222 therein (e.g., as sidewall SEGs), the increased aspect ratio of the opening as the number of interleaved conductive layers 216 and dielectric layers 218 increases would not affect the formation of P-type doped semiconductor layer 220 and semiconductor plugs 222 therein.

Instead of the front side source contacts, 3D memory device 100 can include backside source contacts 231 and 232 above memory stack 214 and in contact with N-well 221 and P-type doped semiconductor layer 220, respectively, as shown in FIG. 1 . Source contacts 231 and 232 and memory stack 214 (and insulating structure 230 therethrough) can be disposed at opposites sides of P-type doped semiconductor layer 220 and thus, viewed as “backside” source contacts. In some embodiments, source contact 232 in contact with P-type doped semiconductor layer 220 is electrically connected to semiconductor channel 228 of channel structure 224 through semiconductor plug 222 of P-type doped semiconductor layer 220. In some embodiments, source contact 231 in contact with N-well 221 is electrically connected to semiconductor channel 228 of channel structure 224 through semiconductor plug 222 of P-type doped semiconductor layer 220. In some embodiments, source contact 232 is not laterally aligned with insulating structure 230 and is approximate to channel structure 224 to reduce the resistance of the electrical connection therebetween. It is understood that although source contact 231 is laterally aligned with insulating structure 230 as shown in FIG. 2 , in some examples, source contact 231 may not be laterally aligned with insulating structure 230, but approximate to channel structure 224 (e.g., laterally between insulating structure 230 and channel structure 224) to reduce the resistance of the electrical connection therebetween as well. As described above, source contacts 231 and 232 can be used to separately control the electron current and hole current during the read operations and erase operations, respectively. Source contacts 231 and 232 can include any suitable types of contacts. In some embodiments, source contacts 231 and 232 include a VIA contact. In some embodiments, source contacts 231 and 232 include a wall-shaped contact extending laterally. Source contacts 231 and 232 can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

As shown in FIG. 2 , 3D memory device 100 can further include a BEOL interconnect layer 233 above and electrically connected to source contacts 231 and 232 for pad-out, e.g., transferring electrical signals between 3D memory device 200 and external circuits. In some embodiments, interconnect layer 233 includes one or more ILD layers 234 on P-type doped semiconductor layer 220 and a redistribution layer 236 on ILD layers 234. The upper end of source contact 231 or 232 is flush with the top surface of ILD layers 234 and the bottom surface of redistribution layer 236. Source contacts 231 and 232 can be electrically separated by on ILD layers 234. In some embodiments, source contact 232 extends vertically through ILD layers 234 into P-type doped semiconductor layer 220 to make an electrical connection with P-type doped semiconductor layer 220. In some embodiments, source contact 231 extends vertically through ILD layers 234 and P-type doped semiconductor layer 220 into N-well 221 to make an electrical connection with N-well. Source contact 231 can include a spacer (e.g., a dielectric layer) surrounding its sidewall to be electrically separated from P-type doped semiconductor layer 220. Redistribution layer 236 can include two electrically separated interconnects: a first interconnect 236-1 in contact with source contact 232 and a second interconnect 236-2 in contact with source contact 231.

ILD layers 234 in interconnect layer 233 can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Redistribution layer 236 in interconnect layer 233 can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, redistribution layer 236 includes Al. In some embodiments, interconnect layer 233 further includes a passivation layer 238 as the outmost layer for passivation and protection of 3D memory device 200. Part of redistribution layer 236 can be exposed from passivation layer 238 as contact pads 240. That is, interconnect layer 233 of 3D memory device 200 can also include contact pads 240 for wire bonding and/or bonding with an interposer.

In some embodiments, second semiconductor structure 204 of 3D memory device 200 further includes contacts 242, 243, and 244 through P-type doped semiconductor layer 220. As P-type doped semiconductor layer 220 can be a thinned substrate, for example, the device layer of a SOI wafer, contacts 242, 243, and 244 are TSCs, according to some embodiments. In some embodiments, contact 242 extends through P-type doped semiconductor layer 220 and ILD layers 234 to be in contact with first interconnect 236-1 of redistribution layer 236, such that P-type doped semiconductor layer 220 is electrically connected to contact 242 through source contact 232 and first interconnect 236-1 of interconnect layer 233. In some embodiments, contact 243 extends through P-type doped semiconductor layer 220 and ILD layers 234 to be in contact with second interconnect 236-2 of redistribution layer 236, such that N-well 221 is electrically connected to contact 243 through source contact 231 and second interconnect 236-2 of interconnect layer 233. In some embodiments, contact 244 extends through P-type doped semiconductor layer 220 and ILD layers 234 to be in contact with contact pad 240. Contacts 242, 243, and 244 each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, at least contacts 243 and 244 each further include a spacer (e.g., a dielectric layer) to electrically separate contacts 243 and 244 from P-type doped semiconductor layer 220.

In some embodiments, 3D memory device 200 further includes peripheral contacts 246, 247, and 248 each extending vertically outside of memory stack 214. Each peripheral contact 246, 247, or 248 can have a depth greater than the depth of memory stack 214 to extend vertically from bonding layer 212 to P-type doped semiconductor layer 220 in a peripheral region that is outside of memory stack 214. In some embodiments, peripheral contact 246 is below and in contact with contact 242, such that P-type doped semiconductor layer 220 is electrically connected to peripheral circuit 208 in first semiconductor structure 202 through at least source contact 232, first interconnect 236-1 of interconnect layer 233, contact 242, and peripheral contact 246. In some embodiments, peripheral contact 247 is below and in contact with contact 243, such that N-well 221 is electrically connected to peripheral circuit 208 in first semiconductor structure 202 through at least source contact 231, second interconnect 236-2 of interconnect layer 233, contact 243, and peripheral contact 247. That is, the electron current and hole current for read operations and erase operations can be separately controlled by peripheral circuits 208 through different electrical connections. In some embodiments, peripheral contact 248 is below and in contact with contact 244, such that peripheral circuit 208 in first semiconductor structure 202 is electrically connected to contact pad 240 for pad-out through at least contact 244 and peripheral contact 248. Peripheral contacts 246, 247, and 248 each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

As shown in FIG. 2 , 3D memory device 200 also includes a variety of local contacts (also known as “C1”) as part of the interconnect structure, which are in contact with a structure in memory stack 214 directly. In some embodiments, the local contacts include channel local contacts 250 each below and in contact with the lower end of respective channel structure 224. Each channel local contact 250 can be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts further include word line local contacts 252 each below and in contact with respective conductive layer 216 (including a word line) at the staircase structure of memory stack 214 for word line fan-out. Local contacts, such as channel local contacts 250 and word line local contacts 252, can be electrically connected to peripheral circuits 208 of first semiconductor structure 202 through at least bonding layers 212 and 210. Local contacts, such as channel local contacts 250 and word line local contacts 252, each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

FIGS. 3A-3N illustrate a fabrication process for forming an exemplary 3D memory device, according to some embodiments of the present disclosure. FIG. 5A illustrates a flowchart of a method 500 for forming an exemplary 3D memory device, according to some embodiments of the present disclosure. FIG. 5B illustrates a flowchart of another method 501 for forming an exemplary 3D memory device, according to some embodiments of the present disclosure. Examples of the 3D memory device depicted in FIGS. 3A-3N, 5A, and 5B include 3D memory device 100 depicted in FIG. 1 . FIGS. 3A-3N, 5A, and 5B will be described together. It is understood that the operations shown in methods 500 and 501 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIGS. 5A and 5B.

Referring to FIG. 5A, method 500 starts at operation 502, in which a peripheral circuit is formed on a first substrate. The first substrate can be a silicon substrate. As illustrated in FIG. 3G, a plurality of transistors are formed on a silicon substrate 350 using a plurality of processes including, but not limited to, photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions (not shown) are formed in silicon substrate 350 by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of the transistors. In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate 350 by wet etching and/or dry etching and thin film deposition. The transistors can form peripheral circuits 352 on silicon substrate 350.

As illustrated in FIG. 3G, a bonding layer 348 is formed above peripheral circuits 352. Bonding layer 348 includes bonding contacts electrically connected to peripheral circuits 352. To form bonding layer 348, an ILD layer is deposited using one or more thin film deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof; the bonding contacts through the ILD layer are formed using wet etching and/or dry etching, e.g., reactive ion etching (RIE), followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

A channel structure extending vertically through a memory stack and an N-type doped semiconductor layer can be formed above a second substrate. Method 500 proceeds to operation 504, as illustrated in FIG. 5A, in which a sacrificial layer on the second substrate, the N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. The second substrate can be a silicon substrate. It is understood that as the second substrate will be removed from the final product, the second substrate may be part of a dummy wafer, for example, a carrier substrate, made of any suitable materials, such as glass, sapphire, plastic, silicon, to name a few, to reduce the cost of the second substrate. In some embodiments, the substrate is a carrier substrate, the sacrificial layer includes a dielectric material, the N-type doped semiconductor layer includes polysilicon, and the dielectric stack includes interleaved stack dielectric layers and stack sacrificial layers. In some embodiments, the stack dielectric layers and stack sacrificial layers are alternatingly deposited on the N-type doped semiconductor layer to form the dielectric stack.

As illustrated in FIG. 3A, a sacrificial layer 304 is formed on a carrier substrate 302, and an N-type doped semiconductor layer 306 is formed on sacrificial layer 304. N-type doped semiconductor layer 306 can include polysilicon doped with N-type dopant(s), such as P, As, or Sb. Sacrificial layer 304 can include any suitable sacrificial materials that can be later selectively removed and are different from the material of N-type doped semiconductor layer 306. In some embodiments, sacrificial layer 304 includes a dielectric material, such as silicon oxide or silicon nitride. To form sacrificial layer 304, silicon oxide or silicon nitride is deposited on carrier substrate 302 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, according to some embodiments. In some embodiments, to form N-type doped semiconductor layer 306, polysilicon is deposited on sacrificial layer 304 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, followed by doping the deposited polysilicon with N-type dopant(s), such as P, As or Sb, using ion implantation and/or thermal diffusion. In some embodiments, to form N-type doped semiconductor layer 306, in-situ doping of N-type dopants, such as P, As, or Sb, is performed when depositing polysilicon on sacrificial layer 304.

As illustrated in FIG. 3B, a dielectric stack 308 including a plurality pairs of a first dielectric layer (referred to herein as “stack sacrificial layer” 312) and a second dielectric layer (referred to herein as “stack dielectric layers” 310, together referred to herein as “dielectric layer pairs”) is formed on N-type doped semiconductor layer 306. Dielectric stack 308 includes interleaved stack sacrificial layers 312 and stack dielectric layers 310, according to some embodiments. Stack dielectric layers 310 and stack sacrificial layers 312 can be alternatively deposited on N-type doped semiconductor layer 306 above carrier substrate 302 to form dielectric stack 308. In some embodiments, each stack dielectric layer 310 includes a layer of silicon oxide, and each stack sacrificial layer 312 includes a layer of silicon nitride. Dielectric stack 308 can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As illustrated in FIG. 3B, a staircase structure can be formed on the edge of dielectric stack 308. The staircase structure can be formed by performing a plurality of so-called “trim-etch” cycles to the dielectric layer pairs of dielectric stack 308 toward carrier substrate 302. Due to the repeated trim-etch cycles applied to the dielectric layer pairs of dielectric stack 308, dielectric stack 308 can have one or more tilted edges and a top dielectric layer pair shorter than the bottom one, as shown in FIG. 3B.

Method 500 proceeds to operation 506, as illustrated in FIG. 5A, in which a channel structure extending vertically through the dielectric stack and the N-type doped semiconductor layer is formed. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the N-type doped semiconductor layer, stopping at the sacrificial layer, is etched, and a memory film and a semiconductor channel are subsequently deposited along a sidewall of the channel hole.

As illustrated in FIG. 3B, a channel hole is an opening extending vertically through dielectric stack 308 and N-type doped semiconductor layer 306. In some embodiments, a plurality of openings are formed, such that each opening becomes the location for growing an individual channel structure 314 in the later process. In some embodiments, fabrication processes for forming the channel hole of channel structure 314 include wet etching and/or dry etching, such as deep RIE (DRIE). Sacrificial layer 304 can act as an etch stop layer to control the gouging variation among different channel holes. For example, the etching of channel holes may be stopped by sacrificial layer 304 without extending further into carrier substrate 302. That is, the lower end of each channel hole (and corresponding channel structure 314) is between the top surface and bottom surface of sacrificial layer 304, according to some embodiments.

As illustrated in FIG. 3B, a memory film including a blocking layer 317, a storage layer 316, and a tunneling layer 315, and a semiconductor channel 318 are subsequently formed in this order along sidewalls and the bottom surface of the channel hole. In some embodiments, blocking layer 317, storage layer 316, and tunneling layer 315 are first deposited along the sidewalls and bottom surface of the channel hole in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to form the memory film. Semiconductor channel 318 then can be formed by depositing a semiconductor material, such as polysilicon (e.g., undoped polysilicon), over tunneling layer 315 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “SONO” structure) are subsequently deposited to form blocking layer 317, storage layer 316, and tunneling layer 315 of the memory film and semiconductor channel 318.

As illustrated in FIG. 3B, a capping layer is formed in the channel hole and over semiconductor channel 318 to completely or partially fill the channel hole (e.g., without or with an air gap). The capping layer can be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A channel plug then can be formed in the top portion of the channel hole. In some embodiments, parts of the memory film, semiconductor channel 318, and the capping layer that are on the top surface of dielectric stack 308 are removed and planarized by CMP, wet etching, and/or dry etching. A recess then can be formed in the top portion of the channel hole by wet etching and/or drying etching parts of semiconductor channel 318 and the capping layer in the top portion of the channel hole. The channel plug then can be formed by depositing semiconductor materials, such as polysilicon, into the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. Channel structure 314 is thereby formed through dielectric stack 308 and N-type doped semiconductor layer 306. Depending on the depth at which the etching of each channel hole stops by sacrificial layer 304, channel structure 314 may extend further into sacrificial layer 304 or stop at the interface between sacrificial layer 304 and N-type doped semiconductor layer 306. Nevertheless, channel structure 314 may not extend further into carrier substrate 302.

Method 500 proceeds to operation 508, as illustrated in FIG. 5A, in which the dielectric stack is replaced with a memory stack, for example, using the so-called “gate replacement” process, such that the channel structure extends vertically through the memory stack and the N-type doped semiconductor layer. In some embodiments, to replace the dielectric stack with the memory stack, an opening extending vertically through the dielectric stack, stopping at the N-type doped semiconductor layer, is etched, and the stack sacrificial layers are replaced with stack conductive layers through the opening to form the memory stack including interleaved the stack dielectric layers and the stack conductive layers.

As illustrated in FIG. 3C, a slit 320 is an opening that extends vertically through dielectric stack 308 and stops at N-type doped semiconductor layer 306. In some embodiments, fabrication processes for forming slit 320 include wet etching and/or dry etching, such as DRIE. A gate replacement then can be performed through slit 320 to replace dielectric stack 308 with a memory stack 330 (shown in FIG. 3E).

As illustrated in FIG. 3D, lateral recesses 322 are first formed by removing stack sacrificial layers 312 (shown in FIG. 3C) through slit 320. In some embodiments, stack sacrificial layers 312 are removed by applying etchants through slit 320, creating lateral recesses 322 interleaved between stack dielectric layers 310. The etchants can include any suitable etchants that etch stack sacrificial layers 312 selective to stack dielectric layers 310.

As illustrated in FIG. 3E, stack conductive layers 328 (including gate electrodes and adhesive layers) are deposited into lateral recesses 322 (shown in FIG. 3D) through slit 320. In some embodiments, a gate dielectric layer 332 is deposited into lateral recesses 322 prior to stack conductive layers 328, such that stack conductive layers 328 are deposited on gate dielectric layer 332. Stack conductive layers 328, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, gate dielectric layer 332, such as a high-k dielectric layer, is formed along the sidewall and at the bottom of slit 320 as well. Memory stack 330 including interleaved stack conductive layers 328 and stack dielectric layers 310 is thereby formed, replacing dielectric stack 308 (shown in FIG. 3D), according to some embodiments.

Method 500 proceeds to operation 510, as illustrated in FIG. 5A, in which an insulating structure extending vertically through the memory stack is formed. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited into the opening to fill the opening. As illustrated in FIG. 3E, an insulating structure 336 extending vertically through memory stack 330 is formed, stopping on the top surface of N-type doped semiconductor layer 306. Insulating structure 336 can be formed by depositing one or more dielectric materials, such as silicon oxide, into slit 320 to fully or partially fill slit 320 (with or without an air gap) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, insulating structure 336 includes gate dielectric layer 332 (e.g., including high-k dielectrics) and a dielectric capping layer 334 (e.g., including silicon oxide).

As illustrated in FIG. 3F, after the formation of insulating structure 336, local contacts, including channel local contacts 344 and word line local contacts 342, and peripheral contacts 338 and 340 are formed. A local dielectric layer can be formed on memory stack 330 by depositing dielectric materials, such as silicon oxide or silicon nitride, using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, on top of memory stack 330. Channel local contacts 344, word line local contacts 342, and peripheral contacts 338 and 340 can be formed by etching contact openings through the local dielectric layer (and any other ILD layers) using wet etching and/or dry etching, e.g., RIE, followed by filling the contact openings with conductive materials using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

As illustrated in FIG. 3F, a bonding layer 346 is formed above channel local contacts 344, word line local contacts 342, and peripheral contacts 338 and 340. Bonding layer 346 includes bonding contacts electrically connected to channel local contacts 344, word line local contacts 342, and peripheral contacts 338 and 340. To form bonding layer 346, an ILD layer is deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, and the bonding contacts are formed through the ILD layer using wet etching and/or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

Method 500 proceeds to operation 512, as illustrated in FIG. 5A, in which the first substrate and the second substrate are bonded in a face-to-face manner, such that the memory stack is above the peripheral circuit. The bonding can include hybrid bonding. As illustrated in FIG. 3G, carrier substrate 302 and components formed thereon (e.g., memory stack 330 and channel structures 314 formed therethrough) are flipped upside down. Bonding layer 346 facing down is bonded with bonding layer 348 facing up, i.e., in a face-to-face manner, thereby forming a bonding interface 354 between carrier substrate 302 and silicon substrate 350, according to some embodiments. In some embodiments, a treatment process, e.g., a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surfaces prior to the bonding. After the bonding, the bonding contacts in bonding layer 346 and the bonding contacts in bonding layer 348 are aligned and in contact with one another, such that memory stack 330 and channel structures 314 formed therethrough can be electrically connected to peripheral circuits 352 and are above peripheral circuits 352.

Method 500 proceeds to operation 514, as illustrated in FIG. 5A, in which the second substrate and the sacrificial layer are removed to expose an end of the channel structure. The removal can be performed from the backside of the second substrate. As illustrated in FIG. 3H, carrier substrate 302 and sacrificial layer 304 (shown in FIG. 3G) are removed from the backside to expose an upper end of channel structure 314. Carrier substrate 302 can be completely removed using CMP, grinding, dry etching, and/or wet etching. In some embodiments, carrier substrate 302 is peeled off. The removal of carrier substrate 302 can be stopped by sacrificial layer 304 underneath due to the different materials thereof to ensure thickness uniformity. In some embodiments in which carrier substrate 302 includes silicon and sacrificial layer 304 includes silicon oxide, carrier substrate 302 is removed using CMP, which can be automatically stopped at the interface between carrier substrate 302 and sacrificial layer 304.

Sacrificial layer 304 then can be selectively removed as well using wet etching with suitable etchants, such as hydrofluoric acid, without etching N-type doped semiconductor layer 306 underneath. As described above, since channel structure 314 does not extend beyond sacrificial layer 304 into carrier substrate 302, the removal of carrier substrate 302 does not affect channel structure 314. The removal of sacrificial layer 304 can expose the upper end of channel structure 314. In some embodiments in which channel structure 314 extends into sacrificial layer 304, the selective etching of sacrificial layer 304 including silicon oxide also removes part of blocking layer 317 including silicon oxide above the top surface of N-type doped semiconductor layer 306, but storage layer 316 including silicon nitride and other layers surrounded by storage layer 316 (e.g., tunneling layer 315) remain intact.

Method 500 proceeds to operation 516, as illustrated in FIG. 5A, in which part of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug. In some embodiments, to replace the part of the channel structure abutting the N-type doped semiconductor layer with the semiconductor plug, part of the memory film abutting the N-type doped semiconductor layer is removed to form a recess surrounding part of the semiconductor channel, the part of the semiconductor channel is doped, and polysilicon is deposited into the recess to form the semiconductor plug surrounding and in contact with the part of the doped semiconductor channel.

As illustrated in FIG. 3I, part of storage layer 316 (shown in FIG. 3H) abutting N-type doped semiconductor layer 306 is removed. In some embodiments, storage layer 316 including silicon nitride is selectively removed using wet etching with suitable etchants, such as phosphoric acid, without etching N-type doped semiconductor layer 306 including polysilicon. The etching of storage layer 316 can be controlled by controlling the etching time and/or etching rate, such that the etching does not continue to affect the rest of storage layer 316 surrounded by memory stack 330.

As illustrated in FIG. 3J, parts of blocking layer 317 and tunneling layer 315 abutting N-type doped semiconductor layer 306 are removed to form a recess 357 surrounding the top portion of semiconductor channel 318 abutting N-type doped semiconductor layer 306. In some embodiments, blocking layer 317 and tunneling layer 315 including silicon oxide are selectively removed using wet etching with suitable etchants, such as hydrofluoric acid, without etching N-type doped semiconductor layer 306 and semiconductor channel 318 including polysilicon. The etching of blocking layer 317 and tunneling layer 315 can be controlled by controlling the etching time and/or etching rate, such that the etching does not continue to affect the rest of blocking layer 317 and tunneling layer 315 surrounded by memory stack 330. As a result, the top portion of the memory film (including blocking layer 317, storage layer 316, and tunneling layer 315) of channel structure 314 abutting N-type doped semiconductor layer 306 is removed to form recess 357, exposing the top portion of semiconductor channel 318, according to some embodiments. In some embodiments, the top portion of semiconductor channel 318 exposed by recess 357 is doped to increase its conductivity. For example, a tilted ion implantation process may be performed to dope the top portion of semiconductor channel 318 (e.g., including polysilicon) exposed by recess 357 with any suitable dopants to a desired doping concentration.

As illustrated in FIG. 3K, a semiconductor plug 359 is formed in recess 357 (shown in FIG. 3J), surrounding and in contact with the doped top portion of semiconductor channel 318. As a result, the top portion of channel structure 314 (shown in FIG. 3H) abutting N-type doped semiconductor layer 306 is thereby replaced with semiconductor plug 359, according to some embodiments. In some embodiments, to form semiconductor plug 359, polysilicon is deposited into recess 357 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof to fill recess 357, followed by a CMP process to remove any excess polysilicon above the top surface of N-type doped semiconductor layer 306. In some embodiments, in-situ doping of N-type dopants, such as P, As, or Sb, is performed when depositing polysilicon into recess 357 to dope semiconductor plug 359. As semiconductor plug 359 and N-type doped semiconductor layer 306 may include the same material, such as polysilicon, and have the same thickness (after the CMP process), semiconductor plug 359 may be viewed as part of N-type doped semiconductor layer 306. Nevertheless, as semiconductor plug 359 is formed in a later process after the formation of the rest of N-type doped semiconductor layer 306 (e.g., shown in FIG. 3A), regardless of whether semiconductor plug 359 is in-situ doped, the doping concentration of semiconductor plug 359 is different from the doping concentration of the rest of N-type doped semiconductor layer 306, according to some embodiments.

As described above, semiconductor plugs 359 in N-type doped semiconductor layer 306 can act as the sidewall SEGs of channel structures 314. Different from known methods that form the sidewall SEGs by etching and deposition processes through slit 320 (e.g., shown in FIG. 3D) extending all the way through dielectric stack 308 with high aspect ratio, semiconductor plugs 359 can be formed from the opposite side of dielectric stack 308/memory stack 330 once carrier substrate 302 is removed, which is not affected by the level of dielectric stack 308/memory stack 330 and the aspect ratio of slit 320. By avoiding the issues introduced by the high aspect ratio of slit 320, the fabrication complexity and cost can be reduced, and the yield can be increased. Moreover, the vertical scalability (e.g., the increasing level of dielectric stack 308/memory stack 330) can be improved as well.

Method 500 proceeds to operation 518, as illustrated in FIG. 5A, in which a source contact is formed above the memory stack and in contact with the N-type doped semiconductor layer. As illustrated in FIG. 3L, one or more ILD layers 356 are formed on N-type doped semiconductor layer 306. ILD layers 356 can be formed by depositing dielectric materials on the top surface of N-type doped semiconductor layer 306 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A source contact opening 358 can be formed through ILD layers 356 into N-type doped semiconductor layer 306. In some embodiments, source contact opening 358 is formed using wet etching and/or dry etching, such as RIE. In some embodiments, source contact opening 358 extends further into the top portion of N-type doped semiconductor layer 306. The etching process through ILD layers 356 may continue to etch part of N-type doped semiconductor layer 306. In some embodiments, a separate etching process is used to etch part of N-type doped semiconductor layer 306 after etching through ILD layers 356.

As illustrated in FIG. 3M, a source contact 364 is formed in source contact opening 358 (shown in FIG. 3L) at the backside of N-type doped semiconductor layer 306. Source contact 364 is above memory stack 330 and in contact with N-type doped semiconductor layer 306, according to some embodiments. In some embodiments, one or more conductive materials are deposited into source contact opening 358 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to fill source contact opening 358 with an adhesive layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, can then be performed to remove the excess conductive materials, such that the top surface of source contact 364 is flush with the top surface of ILD layers 356.

Method 500 proceeds to operation 520, as illustrated in FIG. 5A, in which an interconnect layer is formed above and in contact with the source contact. In some embodiments, a contact is formed through the N-type doped semiconductor layer and in contact with the interconnect layer, such that the N-type doped semiconductor layer is electrically connected to the contact through the source contact and the interconnect layer.

As illustrated in FIG. 3N, a redistribution layer 370 is formed above and in contact with source contact 364. In some embodiments, redistribution layer 370 is formed by depositing a conductive material, such as Al, on the top surfaces of ILD layers 356 and source contact 364 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A passivation layer 372 can be formed on redistribution layer 370. In some embodiments, passivation layer 372 is formed by depositing a dielectric material, such as silicon nitride, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. An interconnect layer 376 including ILD layers 356, redistribution layer 370, and passivation layer 372 is thereby formed, according to some embodiments.

As illustrated in FIG. 3L, contact openings 360 and 361 each extending through ILD layers 356 and N-type doped semiconductor layer 306 are formed. In some embodiments, contact openings 360 and 361 are formed using wet etching and/or dry etching, such as RIE, through ILD layers 356 and N-type doped semiconductor layer 306. In some embodiments, contact openings 360 and 361 are patterned using lithography to be aligned with peripheral contacts 338 and 340, respectively. The etching of contact openings 360 and 361 can stop at the upper ends of peripheral contacts 338 and 340 to expose peripheral contacts 338 and 340. As illustrated in FIG. 3L, a spacer 362 is formed along the sidewalls of contact openings 360 and 361 to electrically separate N-type doped semiconductor layer 306 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, the etching of source contact opening 358 is performed after the formation of spacer 362, such that spacer 362 is not formed along the sidewall of source contact opening 358 to increase the contact area between source contact 364 and N-type doped semiconductor layer 306.

As illustrated in FIG. 3M, contacts 366 and 368 are formed in contact openings 360 and 361, respectively (shown in FIG. 3L) at the backside of N-type doped semiconductor layer 306. Contacts 366 and 368 extend vertically through ILD layers 356 and N-type doped semiconductor layer 306, according to some embodiments. Contacts 366 and 368 and source contact 364 can be formed using the same deposition process to reduce the number of deposition processes. In some embodiments, one or more conductive materials are deposited into contact openings 360 and 361 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to fill contact openings 360 and 361 with an adhesive layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, can then be performed to remove the excess conductive materials, such that the top surfaces of contacts 366 and 368 (and the top surface of source contact 364) are flush with the top surface of ILD layers 356. In some embodiments, as contact openings 360 and 361 are aligned with peripheral contacts 338 and 340, respectively, contacts 366 and 368 are above and in contact with peripheral contacts 338 and 340, respectively, as well.

As illustrated in FIG. 3N, redistribution layer 370 is also formed above and in contact with contact 366. As a result, N-type doped semiconductor layer 306 can be electrically connected to peripheral contact 338 through source contact 364, redistribution layer 370 of interconnect layer 376, and contact 366. In some embodiments, N-type doped semiconductor layer 306 is electrically connected to peripheral circuits 352 through source contact 364, interconnect layer 376, contact 366, peripheral contact 338, and bonding layers 346 and 348.

As illustrated in FIG. 3N, a contact pad 374 is formed above and in contact with contact 368. In some embodiments, part of passivation layer 372 covering contact 368 is removed by wet etching and/or dry etching to expose part of redistribution layer 370 underneath to form contact pad 374. As a result, contact pad 374 for pad-out can be electrically connected to peripheral circuits 352 through contact 368, peripheral contact 340, and bonding layers 346 and 348.

It is understood that the second substrate, sacrificial layer, and N-type doped semiconductor layer described above in method 500 may be replaced by an SOI wafer, which includes a handling layer, a buried oxide layer (also known as a “BOX” layer), and a device layer as described below with respect to method 501. The detail of similar operations between methods 500 and 501 may not be repeated for ease of description. Referring to FIG. 5B, method 501 starts at operation 502, in which a peripheral circuit is formed on a first substrate. The first substrate can be a silicon substrate.

Method 501 proceeds to operation 503, as illustrated in FIG. 5B, in which a device layer of an SOI wafer is doped with an N-type dopant. The SOI wafer can include a handling layer, a buried oxide layer, and a device layer. In some embodiments, the buried oxide layer includes silicon oxide, and the device layer includes single crystalline silicon. As illustrated in FIG. 3A, an SOI wafer 301 includes a handling layer 302 (corresponding to carrier substrate 302 above in describing method 500), a buried oxide layer 304 (corresponding to sacrificial layer 304), and a device layer 306 (corresponding to N-type doped semiconductor layer 306). Device layer 306 can be doped with N-type dopant(s), such as P, As, or Sb, using ion implantation and/or thermal diffusion to become an N-type doped device layer 306. It is understood that the above descriptions related to carrier substrate 302, sacrificial layer 304, and N-type doped semiconductor layer 306 can be similarly applied to handling layer 302, buried oxide layer 304, and doped device layer 306 of SOI wafer 301, respectively, to better understand method 501 below and thus, are not repeated for ease of description.

Method 501 proceeds to operation 505, as illustrated in FIG. 5B, in which a dielectric stack is formed on the doped device layer of the SOI wafer. The dielectric stack can include interleaved stack dielectric layers and stack sacrificial layers. Method 501 proceeds to operation 507, as illustrated in FIG. 5B, in which a channel structure extending vertically through the dielectric stack and the doped device layer is formed. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the doped device layer, stopping at the buried oxide layer, is formed, and a memory film and a semiconductor channel are subsequently deposited along a sidewall of the channel hole. Method 501 proceeds to operation 508, as illustrated in FIG. 5B, in which the dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the doped device layer. In some embodiments, to replace the dielectric stack with the memory stack, an opening extending vertically through the dielectric stack is etched, stopping at the doped device layer, and the stack sacrificial layers are replaced with stack conductive layers through the opening to form the memory stack including interleaved the stack dielectric layers and the stack conductive layers. Method 501 proceeds to operation 510, as illustrated in FIG. 5B, in which an insulating structure extending vertically through the memory stack is formed. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited into the opening to fill the opening.

Method 501 proceeds to operation 513, as illustrated in FIG. 5B, in which the first substrate and the SOI wafer are bonded in a face-to-face manner, such that the memory stack is above the peripheral circuit. The bonding can include hybrid bonding. Method 501 proceeds to operation 515, as illustrated in FIG. 5B, in which the handle layer and the buried oxide layer of the SOI wafer are removed to expose an end of the channel structure. Method 501 proceeds to operation 517, as illustrated in FIG. 5B, in which part of the channel structure abutting the doped device layer is replaced with a semiconductor plug. In some embodiments, to replace the part of the channel structure abutting the doped device layer with the semiconductor plug, part of the memory film abutting the doped device layer is etched to form a recess surrounding part of the semiconductor channel, the part of the semiconductor channel is doped, and polysilicon is deposited into the recess to form the semiconductor plug surrounding and in contact with the part of the doped semiconductor channel.

Method 501 proceeds to operation 519, as illustrated in FIG. 5B, in which a source contact above the memory stack and in contact with the doped device layer is formed. Method 501 proceeds to operation 520, as illustrated in FIG. 5B, in which an interconnect layer above and in contact with the source contact is formed. In some embodiments, a contact is formed through the doped device layer and in contact with the interconnect layer, such that the doped device layer is electrically connected to the contact through the source contact and the interconnect layer.

FIGS. 4A-4O illustrate a fabrication process for forming another exemplary 3D memory device, according to some embodiments of the present disclosure. FIG. 6A illustrates a flowchart of a method 600 for forming another exemplary 3D memory device, according to some embodiments of the present disclosure. FIG. 6B illustrates a flowchart of another method 601 for forming another exemplary 3D memory device, according to some embodiments of the present disclosure. Examples of the 3D memory device depicted in FIGS. 4A-4O, 6A, and 6B include 3D memory device 200 depicted in FIG. 2 . FIGS. 4A-4O, 6A, and 6B will be described together. It is understood that the operations shown in methods 600 and 601 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIGS. 6A and 6B.

Referring to FIG. 6A, method 600 starts at operation 602, in which a peripheral circuit is formed on a first substrate. The first substrate can be a silicon substrate. As illustrated in FIG. 4G, a plurality of transistors are formed on a silicon substrate 450 using a plurality of processes including, but not limited to, photolithography, etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions (not shown) are formed in silicon substrate 450 by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of the transistors. In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate 450 by wet etching and/or dry etching and thin film deposition. The transistors can form peripheral circuits 452 on silicon substrate 450.

As illustrated in FIG. 4G, a bonding layer 448 is formed above peripheral circuits 452. Bonding layer 448 includes bonding contacts electrically connected to peripheral circuits 452. To form bonding layer 448, an ILD layer is deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof; the bonding contacts through the ILD layer are formed using wet etching and/or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

A channel structure extending vertically through a memory stack and a P-type doped semiconductor layer having an N-well can be formed above a second substrate. Method 600 proceeds to operation 604, as illustrated in FIG. 6A, in which a sacrificial layer on the second substrate, the P-type doped semiconductor layer having the N-well on the sacrificial layer, and a dielectric stack on the P-type doped semiconductor layer are subsequently formed. The second substrate can be a silicon substrate. It is understood that as the second substrate will be removed from the final product, the second substrate may be part of a dummy wafer, for example, a carrier substrate, made of any suitable materials, such as glass, sapphire, plastic, silicon, to name a few, to reduce the cost of the second substrate. In some embodiments, the substrate is a carrier substrate, the sacrificial layer includes a dielectric material, the P-type doped semiconductor layer includes polysilicon, and the dielectric stack includes interleaved stack dielectric layers and stack sacrificial layers. In some embodiments, the stack dielectric layers and stack sacrificial layers are alternatingly deposited on the P-type doped semiconductor layer to form the dielectric stack. In some embodiments, prior to forming the dielectric stack, part of the P-type doped semiconductor layer is doped with an N-type dopant to form the N-well.

As illustrated in FIG. 4A, a sacrificial layer 404 is formed on a carrier substrate 402, and a P-type doped semiconductor layer 406 is formed on sacrificial layer 404. P-type doped semiconductor layer 406 can include polysilicon doped with P-type dopant(s), such as B, Ga, or Al. Sacrificial layer 404 can include any suitable sacrificial materials that can be later selectively removed and are different from the material of P-type doped semiconductor layer 406. In some embodiments, sacrificial layer 404 includes a dielectric material, such as silicon oxide or silicon nitride. To form sacrificial layer 404, silicon oxide or silicon nitride is deposited on carrier substrate 402 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, according to some embodiments. In some embodiments, to form P-type doped semiconductor layer 406, polysilicon is deposited on sacrificial layer 404 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, followed by doping the deposited polysilicon with P-type dopant(s), such as B, Ga, or Al, using ion implantation and/or thermal diffusion. In some embodiments, to form P-type doped semiconductor layer 406, in-situ doping of P-type dopants, such as B, Ga, or Al, is performed when depositing polysilicon on sacrificial layer 404.

As illustrated in FIG. 4A, part of P-type doped semiconductor layer 406 is doped with N-type dopant(s), such as P, As, or Sb, to form an N-well 407 in P-type doped semiconductor layer 406. In some embodiments, N-well 407 is formed using ion implantation and/or thermal diffusion. The ion implantation and/or thermal diffusion processes can be controlled to control the thickness of N-well 407, either through the entire thickness of P-type doped semiconductor layer 406 or part thereof.

As illustrated in FIG. 4B, a dielectric stack 408 including a plurality pairs of a first dielectric layer (referred to herein as “stack sacrificial layer” 412) and a second dielectric layer (referred to herein as “stack dielectric layers” 410, together referred to herein as “dielectric layer pairs”) is formed on P-type doped semiconductor layer 406. Dielectric stack 408 includes interleaved stack sacrificial layers 412 and stack dielectric layers 410, according to some embodiments. Stack dielectric layers 410 and stack sacrificial layers 412 can be alternatively deposited on P-type doped semiconductor layer 406 above carrier substrate 402 to form dielectric stack 408. In some embodiments, each stack dielectric layer 410 includes a layer of silicon oxide, and each stack sacrificial layer 412 includes a layer of silicon nitride. Dielectric stack 408 can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As illustrated in FIG. 4B, a staircase structure can be formed on the edge of dielectric stack 408. The staircase structure can be formed by performing a plurality of so-called “trim-etch” cycles to the dielectric layer pairs of dielectric stack 408 toward carrier substrate 402. Due to the repeated trim-etch cycles applied to the dielectric layer pairs of dielectric stack 408, dielectric stack 408 can have one or more tilted edges and a top dielectric layer pair shorter than the bottom one, as shown in FIG. 4B.

Method 600 proceeds to operation 606, as illustrated in FIG. 6A, in which a channel structure extending vertically through the dielectric stack and the P-type doped semiconductor layer is formed. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the P-type doped semiconductor layer, stopping at the sacrificial layer, is etched, and a memory film and a semiconductor channel are subsequently deposited along a sidewall of the channel hole.

As illustrated in FIG. 4B, a channel hole is an opening extending vertically through dielectric stack 408 and P-type doped semiconductor layer 406. In some embodiments, a plurality of openings are formed, such that each opening becomes the location for growing an individual channel structure 414 in the later process. In some embodiments, fabrication processes for forming the channel hole of channel structure 414 include wet etching and/or dry etching, such as DRIE. Sacrificial layer 404 can act as an etch stop layer to control the gouging variation among different channel holes. For example, the etching of channel holes may be stopped by sacrificial layer 404 without extending further into carrier substrate 402. That is, the lower end of each channel hole (and corresponding channel structure 414) is between the top surface and bottom surface of sacrificial layer 404, according to some embodiments.

As illustrated in FIG. 4B, a memory film including a blocking layer 417, a storage layer 416, and a tunneling layer 415, and a semiconductor channel 418 are subsequently formed in this order along sidewalls and the bottom surface of the channel hole. In some embodiments, blocking layer 417, storage layer 416, and tunneling layer 415 are first deposited along the sidewalls and bottom surface of the channel hole in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to form the memory film. Semiconductor channel 418 then can be formed by depositing a semiconductor material, such as polysilicon (e.g., undoped polysilicon), over tunneling layer 415 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “SONO” structure) are subsequently deposited to form blocking layer 417, storage layer 416, and tunneling layer 415 of the memory film and semiconductor channel 418.

As illustrated in FIG. 4B, a capping layer is formed in the channel hole and over semiconductor channel 418 to completely or partially fill the channel hole (e.g., without or with an air gap). The capping layer can be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A channel plug then can be formed in the top portion of the channel hole. In some embodiments, parts of the memory film, semiconductor channel 418, and the capping layer that are on the top surface of dielectric stack 408 are removed and planarized by CMP, wet etching, and/or dry etching. A recess then can be formed in the top portion of the channel hole by wet etching and/or drying etching parts of semiconductor channel 418 and the capping layer in the top portion of the channel hole. The channel plug then can be formed by depositing semiconductor materials, such as polysilicon, into the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. Channel structure 414 is thereby formed through dielectric stack 408 and P-type doped semiconductor layer 406. Depending on the depth at which the etching of each channel hole stops by sacrificial layer 404, channel structure 414 may extend further into sacrificial layer 404 or stop at the interface between sacrificial layer 404 and P-type doped semiconductor layer 406. Nevertheless, channel structure 414 may not extend further into carrier substrate 402.

Method 600 proceeds to operation 608, as illustrated in FIG. 6A, in which the dielectric stack is replaced with a memory stack, for example, using the so-called “gate replacement” process, such that the channel structure extends vertically through the memory stack and the P-type doped semiconductor layer. In some embodiments, to replace the dielectric stack with the memory stack, an opening extending vertically through the dielectric stack, stopping at the P-type doped semiconductor layer, is etched, and the stack sacrificial layers are replaced with stack conductive layers through the opening to form the memory stack including interleaved the stack dielectric layers and the stack conductive layers.

As illustrated in FIG. 4C, a slit 420 is an opening that extends vertically through dielectric stack 408 and stops at P-type doped semiconductor layer 406. In some embodiments, fabrication processes for forming slit 420 include wet etching and/or dry etching, such as DRIE. Although slit 420 is laterally aligned with N-well 407 as shown in FIG. 4C, it is understood that slit 420 may not be laterally aligned with N-well 407 in other examples. A gate replacement then can be performed through slit 420 to replace dielectric stack 408 with a memory stack 430 (shown in FIG. 4E).

As illustrated in FIG. 4D, lateral recesses 422 are first formed by removing stack sacrificial layers 412 (shown in FIG. 4C) through slit 420. In some embodiments, stack sacrificial layers 412 are removed by applying etchants through slit 420, creating lateral recesses 422 interleaved between stack dielectric layers 410. The etchants can include any suitable etchants that etch stack sacrificial layers 412 selective to stack dielectric layers 410.

As illustrated in FIG. 4E, stack conductive layers 428 (including gate electrodes and adhesive layers) are deposited into lateral recesses 422 (shown in FIG. 4D) through slit 420. In some embodiments, a gate dielectric layer 432 is deposited into lateral recesses 422 prior to stack conductive layers 428, such that stack conductive layers 428 are deposited on gate dielectric layer 432. Stack conductive layers 428, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, gate dielectric layer 432, such as a high-k dielectric layer, is formed along the sidewall and at the bottom of slit 420 as well. Memory stack 430 including interleaved stack conductive layers 428 and stack dielectric layers 410 is thereby formed, replacing dielectric stack 408 (shown in FIG. 4D), according to some embodiments.

Method 600 proceeds to operation 610, as illustrated in FIG. 6A, in which an insulating structure extending vertically through the memory stack is formed. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited into the opening to fill the opening. As illustrated in FIG. 4E, an insulating structure 436 extending vertically through memory stack 430 is formed, stopping on the top surface of P-type doped semiconductor layer 406. Insulating structure 436 can be formed by depositing one or more dielectric materials, such as silicon oxide, into slit 420 to fully or partially fill slit 420 (with or without an air gap) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, insulating structure 436 includes gate dielectric layer 432 (e.g., including high-k dielectrics) and a dielectric capping layer 434 (e.g., including silicon oxide).

As illustrated in FIG. 4F, after the formation of insulating structure 436, local contacts, including channel local contacts 444 and word line local contacts 442, and peripheral contacts 438, 439, and 440 are formed. A local dielectric layer can be formed on memory stack 430 by depositing dielectric materials, such as silicon oxide or silicon nitride, using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, on top of memory stack 430. Channel local contacts 444, word line local contacts 442, and peripheral contacts 438, 439, and 440 can be formed by etching contact openings through the local dielectric layer (and any other ILD layers) using wet etching and/or dry etching, e.g., RIE, followed by filling the contact openings with conductive materials using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

As illustrated in FIG. 4F, a bonding layer 446 is formed above channel local contacts 444, word line local contacts 442, and peripheral contacts 438, 439, and 440. Bonding layer 446 includes bonding contacts electrically connected to channel local contacts 444, word line local contacts 442, and peripheral contacts 438, 439, and 440. To form bonding layer 446, an ILD layer is deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, and the bonding contacts are formed through the ILD layer using wet etching and/or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

Method 600 proceeds to operation 612, as illustrated in FIG. 6A, in which the first substrate and the second substrate are bonded in a face-to-face manner, such that the memory stack is above the peripheral circuit. The bonding can include hybrid bonding. As illustrated in FIG. 4G, carrier substrate 402 and components formed thereon (e.g., memory stack 430 and channel structures 414 formed therethrough) are flipped upside down. Bonding layer 446 facing down is bonded with bonding layer 448 facing up, i.e., in a face-to-face manner, thereby forming a bonding interface 454 between carrier substrate 402 and silicon substrate 450, according to some embodiments. In some embodiments, a treatment process, e.g., a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surfaces prior to the bonding. After the bonding, the bonding contacts in bonding layer 446 and the bonding contacts in bonding layer 448 are aligned and in contact with one another, such that memory stack 430 and channel structures 414 formed therethrough can be electrically connected to peripheral circuits 452 and are above peripheral circuits 452.

Method 600 proceeds to operation 614, as illustrated in FIG. 6A, in which the second substrate and the sacrificial layer are removed to expose an end of the channel structure. The removal can be performed from the backside of the second substrate. As illustrated in FIG. 4H, carrier substrate 402 and sacrificial layer 404 (shown in FIG. 4G) are removed from the backside to expose an upper end of channel structure 414. Carrier substrate 402 can be completely removed using CMP, grinding, dry etching, and/or wet etching. In some embodiments, carrier substrate 402 is peeled off. The removal of carrier substrate 402 can be stopped by sacrificial layer 404 underneath due to the different materials thereof to ensure thickness uniformity. In some embodiments in which carrier substrate 402 includes silicon and sacrificial layer 304 includes silicon oxide, carrier substrate 402 is removed using CMP, which can be automatically stopped at the interface between carrier substrate 402 and sacrificial layer 404.

Sacrificial layer 404 then can be selectively removed as well using wet etching with suitable etchants, such as hydrofluoric acid, without etching P-type doped semiconductor layer 406 underneath. As described above, since channel structure 414 does not extend beyond sacrificial layer 404 into carrier substrate 402, the removal of carrier substrate 402 does not affect channel structure 414. The removal of sacrificial layer 404 can expose the upper end of channel structure 414. In some embodiments in which channel structure 414 extends into sacrificial layer 404, the selective etching of sacrificial layer 404 including silicon oxide also removes part of blocking layer 417 including silicon oxide above the top surface of P-type doped semiconductor layer 406, but storage layer 416 including silicon nitride and other layers surrounded by storage layer 416 (e.g., tunneling layer 415) remain intact.

Method 600 proceeds to operation 616, as illustrated in FIG. 6A, in which part of the channel structure abutting the P-type doped semiconductor layer is replaced with a semiconductor plug. In some embodiments, to replace the part of the channel structure abutting the P-type doped semiconductor layer with the semiconductor plug, part of the memory film abutting the P-type doped semiconductor layer is removed to form a recess surrounding part of the semiconductor channel, the part of the semiconductor channel is doped, and polysilicon is deposited into the recess to form the semiconductor plug surrounding and in contact with the part of the doped semiconductor channel.

As illustrated in FIG. 4I, part of storage layer 416 (shown in FIG. 4H) abutting P-type doped semiconductor layer 406 is removed. In some embodiments, storage layer 416 including silicon nitride is selectively removed using wet etching with suitable etchants, such as phosphoric acid, without etching P-type doped semiconductor layer 406 including polysilicon. The etching of storage layer 416 can be controlled by controlling the etching time and/or etching rate, such that the etching does not continue to affect the rest of storage layer 416 surrounded by memory stack 430.

As illustrated in FIG. 4J, parts of blocking layer 417 and tunneling layer 415 abutting P-type doped semiconductor layer 406 are removed to form a recess 457 surrounding the top portion of semiconductor channel 418 abutting P-type doped semiconductor layer 406. In some embodiments, blocking layer 417 and tunneling layer 415 including silicon oxide are selectively removed using wet etching with suitable etchants, such as hydrofluoric acid, without etching P-type doped semiconductor layer 406 and semiconductor channel 418 including polysilicon. The etching of blocking layer 417 and tunneling layer 415 can be controlled by controlling the etching time and/or etching rate, such that the etching does not continue to affect the rest of blocking layer 417 and tunneling layer 415 surrounded by memory stack 430. As a result, the top portion of the memory film (including blocking layer 417, storage layer 416, and tunneling layer 415) of channel structure 414 abutting P-type doped semiconductor layer 406 is removed to form recess 457, exposing the top portion of semiconductor channel 418, according to some embodiments. In some embodiments, the top portion of semiconductor channel 418 exposed by recess 457 is doped to increase its conductivity. For example, a tilted ion implantation process may be performed to dope the top portion of semiconductor channel 418 (e.g., including polysilicon) exposed by recess 457 with any suitable dopants to a desired doping concentration.

As illustrated in FIG. 4K, a semiconductor plug 459 is formed in recess 457 (shown in FIG. 4J), surrounding and in contact with the doped top portion of semiconductor channel 418. As a result, the top portion of channel structure 414 (shown in FIG. 4H) abutting P-type doped semiconductor layer 406 is thereby replaced with semiconductor plug 459, according to some embodiments. In some embodiments, to form semiconductor plug 459, polysilicon is deposited into recess 457 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof to fill recess 457, followed by a CMP process to remove excess polysilicon above the top surface of P-type doped semiconductor layer 406. In some embodiments, in-situ doping of P-type dopants, such as B, Ga, or Al, is performed when depositing polysilicon into recess 457 to dope semiconductor plug 459. As semiconductor plug 459 and P-type doped semiconductor layer 406 may include the same material, such as polysilicon, and have the same thickness (after the CMP process), semiconductor plug 459 may be viewed as part of P-type doped semiconductor layer 406. Nevertheless, as semiconductor plug 459 is formed in a later process after the formation of the rest of P-type doped semiconductor layer 406 (e.g., shown in FIG. 4A), regardless of whether semiconductor plug 459 is in-situ doped, the doping concentration of semiconductor plug 459 is different from the doping concentration of the rest of P-type doped semiconductor layer 406, according to some embodiments.

As described above, semiconductor plugs 459 in P-type doped semiconductor layer 406 can act as the sidewall SEGs of channel structures 414. Different from known methods that form the sidewall SEGs by etching and deposition processes through slit 420 (e.g., shown in FIG. 4D) extending all the way through dielectric stack 408 with high aspect ratio, semiconductor plugs 459 can be formed from the opposite side of dielectric stack 408/memory stack 430 once carrier substrate 402 is removed, which is not affected by the level of dielectric stack 408/memory stack 430 and the aspect ratio of slit 420. By avoiding the issues introduced by the high aspect ratio of slit 420, the fabrication complexity and cost can be reduced, and the yield can be increased. Moreover, the vertical scalability (e.g., the increasing level of dielectric stack 408/memory stack 430) can be improved as well.

Method 600 proceeds to operation 618, as illustrated in FIG. 6A, in which a first source contact is formed above the memory stack and in contact with the P-type doped semiconductor layer, and a second source contact is formed above the memory stack and in contact with the N-well. As illustrated in FIG. 4L, one or more ILD layers 456 are formed on P-type doped semiconductor layer 406. ILD layers 456 can be formed by depositing dielectric materials on the top surface of P-type doped semiconductor layer 406 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

As illustrated in FIG. 4M, a source contact opening 458 can be formed through ILD layers 456 into P-type doped semiconductor layer 406. In some embodiments, source contact opening 458 is formed using wet etching and/or dry etching, such as RIE. In some embodiments, source contact opening 458 extends further into the top portion of P-type doped semiconductor layer 406. The etching process through ILD layers 456 may continue to etch part of P-type doped semiconductor layer 406. In some embodiments, a separate etching process is used to etch part of P-type doped semiconductor layer 406 after etching through ILD layers 456.

As illustrated in FIG. 4M, a source contact opening 465 can be formed through ILD layers 456 into N-well 407. In some embodiments, source contact opening 465 is formed using wet etching and/or dry etching, such as RIE. In some embodiments, source contact opening 465 extends further into the top portion of N-well 407. The etching process through ILD layers 456 may continue to etch part of N-well 407. In some embodiments, a separate etching process is used to etch part of N-well 407 after etching through ILD layers 456. The etching of source contact opening 458 can be performed after the etching of source contact opening 465 or vice versa. It is understood that in some examples, source contact openings 458 and 465 may be etched by the same etching process to reduce the number of etching processes.

As illustrated in FIG. 4N, source contacts 464 and 478 are formed in source contact openings 458 and 465, respectively, (shown in FIG. 4M) at the backside of P-type doped semiconductor layer 406. Source contact 464 is above memory stack 430 and in contact with P-type doped semiconductor layer 406, according to some embodiments. Source contact 478 is above memory stack 430 and in contact with N-well 407, according to some embodiments. In some embodiments, one or more conductive materials are deposited into source contact openings 458 and 465 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to fill source contact openings 458 and 465 with adhesive layers (e.g., TiN) and conductor layers (e.g., W). A planarization process, such as CMP, can then be performed to remove the excess conductive materials, such that the top surfaces of source contacts 464 and 478 are flush with one another as well as flush with the top surface of ILD layers 456. It is understood that in some examples, source contacts 464 and 478 may be formed by the same deposition and CMP processes to reduce the number of fabrication processes.

Method 600 proceeds to operation 620, as illustrated in FIG. 6A, in which an interconnect layer is formed above and in contact with the first and second source contacts. In some embodiments, the interconnect layer includes a first interconnect and a second interconnect above and in contact with the first and second source contacts, respectively.

As illustrated in FIG. 4O, a redistribution layer 470 is formed above and in contact with source contacts 464 and 478. In some embodiments, redistribution layer 470 is formed by depositing a conductive material, such as Al, on the top surfaces of ILD layers 456 and source contact 364 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, redistribution layer 470 is patterned by lithography and etching processes to form a first interconnect 470-1 above and in contact with source contact 464 and a second interconnect 470-2 above and in contact with source contact 478. First and second interconnects 470-1 and 470-2 can be electrically separated from one another. A passivation layer 472 can be formed on redistribution layer 470. In some embodiments, passivation layer 472 is formed by depositing a dielectric material, such as silicon nitride, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. An interconnect layer 476 including ILD layers 456, redistribution layer 470, and passivation layer 472 is thereby formed, according to some embodiments.

As illustrated in FIG. 4L, contact openings 460, 461, and 463 each extending through ILD layers 456 and P-type doped semiconductor layer 406 are formed. In some embodiments, contact openings 460, 461, and 463 are formed using wet etching and/or dry etching, such as RIE, through ILD layers 456 and P-type doped semiconductor layer 406. In some embodiments, contact openings 460, 461, and 463 are patterned using lithography to be aligned with peripheral contacts 438, 440, and 439, respectively. The etching of contact openings 460, 461, and 463 can stop at the upper ends of peripheral contacts 438, 439, and 440 to expose peripheral contacts 438, 439, and 440. The etching of contact openings 460, 461, and 463 can be performed by the same etching process to reduce the number of etching processes. It is understood that due to the different etching depths, the etching of contact openings 460, 461, and 463 may be performed prior to the etching of source contact opening 465, or vice versa, but not at the same time.

As illustrated in FIG. 4M, a spacer 462 is formed along the sidewalls of contact openings 460, 461, and 463 as well as source contact opening 465 to electrically separate P-type doped semiconductor layer 406 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, spacers 462 are formed along the sidewalls of contact openings 460, 461, and 463 as well as source contact opening 465 by the same deposition process to reduce the number of fabrication processes. In some embodiments, the etching of source contact opening 458 is performed after the formation of spacer 362, such that spacer 362 is not formed along the sidewall of source contact opening 358 to increase the contact area between source contact 364 and N-type doped semiconductor layer 306.

As illustrated in FIG. 4N, contacts 466, 468, and 469 are formed in contact openings 460, 461, and 463, respectively (shown in FIG. 4M) at the backside of P-type doped semiconductor layer 406. Contacts 466, 468, and 469 extend vertically through ILD layers 456 and P-type doped semiconductor layer 406, according to some embodiments. Contacts 466, 468, and 469 as well as source contacts 464 and 478 can be formed using the same deposition process to reduce the number of deposition processes. In some embodiments, one or more conductive materials are deposited into contact openings 460, 461, and 463 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to fill contact openings 460, 461, and 463 with an adhesive layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, can then be performed to remove the excess conductive materials, such that the top surfaces of contacts 466, 468, and 469 (and the top surfaces of source contact 464 and 478) are flush with the top surface of ILD layers 456. In some embodiments, as contact openings 460, 461, and 463 are aligned with peripheral contacts 438, 440, and 439, respectively, contacts 466, 468, and 469 are above and in contact with peripheral contacts 438, 440, and 439, respectively, as well.

As illustrated in FIG. 4O, first interconnect 470-1 of redistribution layer 470 is formed above and in contact with contact 466. As a result, P-type doped semiconductor layer 406 can be electrically connected to peripheral contact 438 through source contact 464, first interconnect 470-1 of interconnect layer 476, and contact 466. In some embodiments, P-type doped semiconductor layer 406 is electrically connected to peripheral circuits 452 through source contact 464, first interconnect 470-1 of interconnect layer 476, contact 466, peripheral contact 438, and bonding layers 446 and 448. Similarly, second interconnect 470-2 of redistribution layer 470 is formed above and in contact with contact 469. As a result, N-well 407 can be electrically connected to peripheral contact 438 through source contact 478, second interconnect 470-2 of interconnect layer 476, and contact 469. In some embodiments, N-well 407 is electrically connected to peripheral circuits 452 through source contact 478, second interconnect 470-2 of interconnect layer 476, contact 469, peripheral contact 439, and bonding layers 446 and 448.

As illustrated in FIG. 4O, a contact pad 474 is formed above and in contact with contact 468. In some embodiments, part of passivation layer 472 covering contact 468 is removed by wet etching and/or dry etching to expose part of redistribution layer 470 underneath to form contact pad 474. As a result, contact pad 474 for pad-out can be electrically connected to peripheral circuits 452 through contact 468, peripheral contact 440, and bonding layers 446 and 448.

It is understood that the second substrate, sacrificial layer, and P-type doped semiconductor layer described above in method 600 may be replaced by an SOI wafer, which includes a handling layer, a buried oxide layer (also known as a “BOX” layer), and a device layer as described below with respect to method 601. The detail of similar operations between methods 600 and 601 may not be repeated for ease of description. Referring to FIG. 6B, method 601 starts at operation 602, in which a peripheral circuit is formed on a first substrate. The first substrate can be a silicon substrate.

Method 601 proceeds to operation 603, as illustrated in FIG. 6B, in which a device layer of an SOI wafer is doped with a P-type dopant. The SOI wafer can include a handling layer, a buried oxide layer, and a device layer. In some embodiments, the buried oxide layer includes silicon oxide, and the device layer includes single crystalline silicon. Method 601 proceeds to operation 605, as illustrated in FIG. 6B, in which part of the doped device layer is doped with an N-type dopant to form an N-well in the doped device layer.

As illustrated in FIG. 4A, an SOI wafer 401 includes a handling layer 402 (corresponding to carrier substrate 402 above in describing method 600), a buried oxide layer 404 (corresponding to sacrificial layer 404), and a device layer 406 (corresponding to P-type doped semiconductor layer 406). Device layer 406 can be doped with P-type dopant(s), such as P, As, or Sb, using ion implantation and/or thermal diffusion to become a P-type doped device layer 406. Part of doped device layer 406 can be further doped with N-type dopant(s), such as B, Ga, or Al, using ion implantation and/or thermal diffusion to form N-well 407. It is understood that the above descriptions related to carrier substrate 402, sacrificial layer 404, and P-type doped semiconductor layer 406 can be similarly applied to handling layer 402, buried oxide layer 404, and doped device layer 406 of SOI wafer 401, respectively, to better understand method 601 below and thus, are not repeated for ease of description.

Method 601 proceeds to operation 607, as illustrated in FIG. 6B, in which a dielectric stack is formed on the doped device layer of the SOI wafer. The dielectric stack can include interleaved stack dielectric layers and stack sacrificial layers. Method 601 proceeds to operation 609, as illustrated in FIG. 6B, in which a channel structure extending vertically through the dielectric stack and the doped device layer is formed. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the doped device layer, stopping at the buried oxide layer, is formed, and a memory film and a semiconductor channel are subsequently deposited along a sidewall of the channel hole. Method 601 proceeds to operation 608, as illustrated in FIG. 6B, in which the dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the doped device layer. In some embodiments, to replace the dielectric stack with the memory stack, an opening extending vertically through the dielectric stack is etched, stopping at the doped device layer, and the stack sacrificial layers are replaced with stack conductive layers through the opening to form the memory stack including interleaved the stack dielectric layers and the stack conductive layers. Method 601 proceeds to operation 610, as illustrated in FIG. 6B, in which an insulating structure extending vertically through the memory stack is formed. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited into the opening to fill the opening.

Method 601 proceeds to operation 613, as illustrated in FIG. 6B, in which the first substrate and the SOI wafer are bonded in a face-to-face manner, such that the memory stack is above the peripheral circuit. The bonding can include hybrid bonding. Method 601 proceeds to operation 615, as illustrated in FIG. 6B, in which the handle layer and the buried oxide layer of the SOI wafer are removed to expose an end of the channel structure. Method 601 proceeds to operation 617, as illustrated in FIG. 6B, in which part of the channel structure abutting the doped device layer is replaced with a semiconductor plug. In some embodiments, to replace the part of the channel structure abutting the doped device layer with the semiconductor plug, part of the memory film abutting the doped device layer is etched to form a recess surrounding part of the semiconductor channel, the part of the semiconductor channel is doped, and polysilicon is deposited into the recess to form the semiconductor plug surrounding and in contact with the part of the doped semiconductor channel.

Method 601 proceeds to operation 619, as illustrated in FIG. 6B, in which a first source contact above the memory stack and in contact with the doped device layer is formed, and a second source contact above the memory stack and in contact with the N-well is formed. Method 601 proceeds to operation 621, as illustrated in FIG. 6B, in which an interconnect layer above and in contact with the first and second source contacts is formed. In some embodiments, the interconnect layer includes a first interconnect above and in contact with the first source contact, and a second interconnect above and in contact with the second source contact. In some embodiments, a first contact is formed through the doped device layer and in contact with the first interconnect, such that the doped device layer is electrically connected to the first contact through the first source contact and the first interconnect. In some embodiments, a second contact is formed through the doped device layer and in contact with the second interconnect, such that the N-well is electrically connected to the second contact through the second source contact and the second interconnect.

According to one aspect of the present disclosure, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, an N-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, and a source contact above the memory stack and in contact with the N-type doped semiconductor layer. An upper end of each of the plurality of channel structures is flush with or below a top surface of the N-type doped semiconductor layer.

In some embodiments, the N-type doped semiconductor layer includes polysilicon.

In some embodiments, the N-type doped semiconductor layer includes single crystalline silicon.

In some embodiments, each of the channel structures includes a memory film and a semiconductor channel, and an upper end of the memory film is below an upper end of the semiconductor channel.

In some embodiments, the upper end of the memory film is below the top surface of the N-type doped semiconductor layer, and the upper end of the semiconductor channel is flush with or below the top surface of the N-type doped semiconductor layer.

In some embodiments, a portion of the semiconductor channel extending into the N-type doped semiconductor layer includes doped polysilicon.

In some embodiments, the N-type doped semiconductor layer includes a semiconductor plug surrounding and in contact with the portion of the semiconductor channel, and a doping concentration of the semiconductor plugs is different from a doping concentration of the rest of the N-type doped semiconductor layer.

In some embodiments, the 3D memory device further includes an interconnect layer above and electrically connected to the source contact.

In some embodiments, the 3D memory device further includes a first contact through the N-type doped semiconductor layer. The N-type doped semiconductor layer is electrically connected to the peripheral circuit through at least the source contact, the interconnect layer, and the first contact, according to some embodiments.

In some embodiments, the 3D memory device further includes a second contact through the N-type doped semiconductor layer. The interconnect layer includes a contact pad electrically connected to the second contact, according to some embodiments.

In some embodiments, the 3D memory device further includes an insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks.

In some embodiments, the insulating structure is filled with one or more dielectric materials.

In some embodiments, a top surface of the insulating structure is flush with a bottom surface of the N-type doped semiconductor layer.

In some embodiments, the 3D memory device further includes a bonding interface between the peripheral circuit and the memory stack.

According to another aspect of the present disclosure, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, an N-type doped semiconductor layer above the memory stack, and a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer. Each of the plurality of channel structures includes a memory film and a semiconductor channel. An upper end of the memory film is below an upper end of the semiconductor channel. The N-type doped semiconductor layer includes a semiconductor plug surrounding and in contact with a portion of the semiconductor channel. A doping concentration of the semiconductor plugs is different from a doping concentration of the rest of the N-type doped semiconductor layer.

In some embodiments, the semiconductor plugs include polysilicon, and the rest of the N-type doped semiconductor layer includes polysilicon.

In some embodiments, the semiconductor plugs include polysilicon, and the rest of the N-type doped semiconductor layer includes single crystalline silicon.

In some embodiments, the 3D memory device further includes an insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks.

In some embodiments, the insulating structure is filled with one or more dielectric materials.

In some embodiments, a top surface of the insulating structure is flush with a bottom surface of the N-type doped semiconductor layer.

In some embodiments, the 3D memory device further includes a source contact above the memory stack and in contact with the N-type doped semiconductor layer.

In some embodiments, the 3D memory device further includes a peripheral circuit above the substrate, and a bonding interface between the peripheral circuit and the memory stack.

In some embodiments, the 3D memory device further includes an interconnect layer above and electrically connected to the source contact.

In some embodiments, the N-type doped semiconductor layer is electrically connected to the peripheral circuit through at least the source contact and the interconnect layer.

According to still another aspect of the present disclosure, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes a memory stack including interleaved conductive layers and dielectric layers, an N-type doped semiconductor layer, and a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer and electrically connected to the peripheral circuit. The N-type doped semiconductor layer includes a semiconductor plug surrounding a portion of each of the plurality of channel structures extending into the N-type doped semiconductor layer. A doping concentration of the semiconductor plugs is different from a doping concentration of the rest of the N-type doped semiconductor layer.

In some embodiments, second semiconductor structure further includes an insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks.

In some embodiments, the insulating structure is filled with one or more dielectric materials.

In some embodiments, the insulating structure does not extend vertically into the N-type doped semiconductor layer.

In some embodiments, the second semiconductor structure further includes a source contact in contact with the N-type doped semiconductor layer.

In some embodiments, the second semiconductor structure further includes an interconnect layer, and each of the channel structures does not extend beyond the N-type doped semiconductor layer.

In some embodiments, the semiconductor plugs include polysilicon, and the rest of the N-type doped semiconductor layer includes polysilicon.

In some embodiments, the semiconductor plugs include polysilicon, and the rest of the N-type doped semiconductor layer includes single crystalline silicon.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. 

What is claimed is:
 1. A three-dimensional (3D) memory device, comprising: a memory stack comprising interleaved conductive layers and dielectric layers; a semiconductor layer above the memory stack; a plurality of channel structures each extending vertically through the memory stack, a semiconductor plug, in contact with the semiconductor layer, surrounding an end of one of the channel structures; and a source contact above the memory stack and in contact with the semiconductor layer, wherein the source contact is electrically connected with the one of the channel structures, at least a portion of the source contact being buried within the semiconductor layer.
 2. The 3D memory device of claim 1, wherein: a material of the semiconductor plug is different from a material of the semiconductor layer.
 3. The 3D memory device of claim 1, wherein: a doping concentration of the semiconductor plug is different from a doping concentration of the semiconductor layer.
 4. The 3D memory device of claim 1, wherein: a top portion of the one of the channel structures is flush with or below a top surface of the semiconductor layer.
 5. The 3D memory device of claim 1, further comprising: a peripheral circuit on a substrate, wherein the one of the channel structures is electrically connected with the peripheral circuit through at least the semiconductor layer and the source contact.
 6. The 3D memory device of claim 5, further comprising: a bonding interface between the peripheral circuit and the plurality of channel structures, wherein the one of the channel structures is electrically connected with the peripheral circuit through at least the source contact, the semiconductor layer, and the bonding interface.
 7. The 3D memory device of claim 6, further comprising: a peripheral contact extending vertically outside the memory stack and connected to the peripheral circuit; and an interconnect layer above the semiconductor layer, wherein the one of the channel structures is electrically connected with the peripheral circuit through at least the source contact, the semiconductor layer, the interconnect layer, the peripheral contact, and the bonding interface.
 8. The 3D memory device of claim 1, wherein: the one of the channel structures comprises a semiconductor channel; and a doping concentration of a top portion of the semiconductor channel surrounded by the semiconductor plug is different from a doping concentration of a remaining portion of the semiconductor channel.
 9. The 3D memory device, of claim 1, further comprising: an insulating structure extending vertically through the memory stack and filled with at least one dielectric material.
 10. The 3D memory device of claim 1, wherein: the semiconductor layer comprises an N-type doped semiconductor layer or a P-type doped semiconductor layer.
 11. The 3D memory device of claim 1, wherein: the semiconductor layer is an N-type doped semiconductor layer; and the 3D memory device further comprises an insulating structure extending vertically through the memory stack, the N-type doped semiconductor layer being in contact with a dielectric material of the insulating structure.
 12. The 3D memory device of claim 1, wherein: the semiconductor layer is a P-type doped semiconductor layer, and the source contact is a first source contact; and the 3D memory device further comprises: an N-well arranged in the P-type doped semiconductor layer; and a second source contact extending into the N-well to have an electrical connection with the N-well.
 13. The 3D memory device of claim 12, further comprising: an insulating structure extending vertically through the memory stack, wherein the N-well is aligned with the insulating structure vertically.
 14. The 3D memory device of claim 12, further comprising: an interconnect layer above the semiconductor layer; a peripheral circuit on a substrate; and a peripheral contact extending vertically outside the memory stack and connected with the peripheral circuit, wherein the N-well is electrically connected with the peripheral circuit through at least the second source contact, the interconnect layer, and the peripheral contact.
 15. A three-dimensional (3D) memory device, comprising: a peripheral circuit; a memory stack arranged above the peripheral circuit and comprising interleaved conductive layers and dielectric layers; a semiconductor layer above the memory stack; a plurality of channel structures each extending vertically through the memory stack, a semiconductor plug, in contact with the semiconductor layer, surrounding an end of one of the channel structures; and a source contact above the memory stack and in contact with the semiconductor layer, wherein the peripheral circuit is electrically connected with the one of the channel structures.
 16. The 3D memory device of claim 15, wherein: the peripheral circuit is arranged in a first semiconductor structure; and the memory stack is arranged in a second semiconductor structure, wherein: the first semiconductor structure and the second semiconductor structure are connected through a bonding interface; and the one of the channel structures is electrically connected with the peripheral circuit through at least the source contact, the semiconductor layer, the semiconductor plug, and the bonding interface.
 17. The 3D memory device, of claim 15, wherein: the one of the channel structures comprises a semiconductor channel; and a doping concentration of a top portion of the semiconductor channel surrounded by the semiconductor plug is different from a doping concentration of a remaining portion of the semiconductor channel.
 18. A three-dimensional (3D) memory device, comprising: a first semiconductor structure comprising a peripheral circuit; a second semiconductor structure comprising: a memory stack comprising interleaved conductive layers and dielectric layers; a semiconductor layer above the memory stack; a plurality of channel structures each extending vertically through the memory stack; and a source contact arranged above the memory stack and buried within the semiconductor layer; and a bonding interface between the first semiconductor structure and the second semiconductor structure, wherein the one of the channel structures is electrically connected with the peripheral circuit through at least the semiconductor layer, the source contact, and the bonding interface.
 19. The 3D memory device of claim 18, wherein: an insulating structure extending vertically through the memory stack and filled with at least one dielectric material.
 20. The 3D memory device of claim 18, further comprising: an interconnect layer above the semiconductor layer, wherein the one of the channel structures is electrically connected with the peripheral circuit through at least the semiconductor layer, the source contact, the interconnect layer, and the bonding interface. 